1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* DPU Layer registers offset */
35  * @base: DPU controller base address
46 	void __iomem *base;  member
64 	struct drm_crtc base;  member
71 	return container_of(crtc, struct sprd_dpu, base);  in to_sprd_crtc()
75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits)  in dpu_reg_set()  argument
77 	u32 bits = readl_relaxed(ctx->base + offset);  in dpu_reg_set()
79 	writel(bits | set_bits, ctx->base + offset);  in dpu_reg_set()
83 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits)  in dpu_reg_clr()  argument
85 	u32 bits = readl_relaxed(ctx->base + offset);  in dpu_reg_clr()
87 	writel(bits & ~clr_bits, ctx->base + offset);  in dpu_reg_clr()
91 layer_reg_rd(struct dpu_context *ctx, u32 offset, int index)  in layer_reg_rd()  argument
93 	u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;  in layer_reg_rd()
95 	return readl(ctx->base + layer_offset);  in layer_reg_rd()
99 layer_reg_wr(struct dpu_context *ctx, u32 offset, u32 cfg_bits, int index)  in layer_reg_wr()  argument
101 	u32 layer_offset =  offset + index * DPU_LAY_REG_OFFSET;  in layer_reg_wr()
103 	writel(cfg_bits, ctx->base + layer_offset);  in layer_reg_wr()