Lines Matching +full:0 +full:x434
12 #define RK3288_LVDS_CH0_REG0 0x00
20 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
22 #define RK3288_LVDS_CH0_REG1 0x04
28 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)
30 #define RK3288_LVDS_CH0_REG2 0x08
38 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)
40 #define RK3288_LVDS_CH0_REG3 0x0c
41 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff
43 #define RK3288_LVDS_CH0_REG4 0x10
49 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
51 #define RK3288_LVDS_CH0_REG5 0x14
57 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)
59 #define RK3288_LVDS_CFG_REGC 0x30
60 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00
61 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff
63 #define RK3288_LVDS_CH0_REGD 0x34
64 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f
66 #define RK3288_LVDS_CH0_REG20 0x80
67 #define RK3288_LVDS_CH0_REG20_MSB 0x45
68 #define RK3288_LVDS_CH0_REG20_LSB 0x44
70 #define RK3288_LVDS_CFG_REG21 0x84
71 #define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92
72 #define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00
73 #define RK3288_LVDS_CH1_OFFSET 0x100
75 #define RK3288_LVDS_GRF_SOC_CON6 0x025C
76 #define RK3288_LVDS_GRF_SOC_CON7 0x0260
80 (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
88 #define LVDS_FMT_MASK (0x07 << 16)
99 #define LVDS_24BIT (0 << 1)
101 #define LVDS_FORMAT_VESA (0 << 0)
102 #define LVDS_FORMAT_JEIDA (1 << 0)
104 #define LVDS_VESA_24 0
111 #define PX30_LVDS_GRF_PD_VO_CON0 0x434
116 #define PX30_LVDS_GRF_PD_VO_CON1 0x438