Lines Matching +full:1 +full:x64 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author:Mark Yao <mark.yao@rock-chips.com>
15 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
17 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
18 #define VOP2_FEATURE_HAS_VO0_GRF BIT(1)
19 #define VOP2_FEATURE_HAS_VO1_GRF BIT(2)
20 #define VOP2_FEATURE_HAS_VOP_GRF BIT(3)
21 #define VOP2_FEATURE_HAS_SYS_PMU BIT(4)
23 #define WIN_FEATURE_AFBDC BIT(0)
24 #define WIN_FEATURE_CLUSTER BIT(1)
53 #define VOP2_PD_CLUSTER0 BIT(0)
54 #define VOP2_PD_CLUSTER1 BIT(1)
55 #define VOP2_PD_CLUSTER2 BIT(2)
56 #define VOP2_PD_CLUSTER3 BIT(3)
57 #define VOP2_PD_DSC_8K BIT(5)
58 #define VOP2_PD_DSC_4K BIT(6)
59 #define VOP2_PD_ESMART BIT(7)
190 #define FS_NEW_INTR BIT(4)
191 #define ADDR_SAME_INTR BIT(5)
192 #define LINE_FLAG1_INTR BIT(6)
193 #define WIN0_EMPTY_INTR BIT(7)
194 #define WIN1_EMPTY_INTR BIT(8)
195 #define WIN2_EMPTY_INTR BIT(9)
196 #define WIN3_EMPTY_INTR BIT(10)
197 #define HWC_EMPTY_INTR BIT(11)
198 #define POST_BUF_EMPTY_INTR BIT(12)
199 #define PWM_GEN_INTR BIT(13)
200 #define DMA_FINISH_INTR BIT(14)
201 #define FS_FIELD_INTR BIT(15)
202 #define FE_INTR BIT(16)
203 #define WB_UV_FIFO_FULL_INTR BIT(17)
204 #define WB_YRGB_FIFO_FULL_INTR BIT(18)
205 #define WB_COMPLETE_INTR BIT(19)
292 #define RK3568_VP_BCSH_BCS 0x64
344 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
373 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
415 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15)
417 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31)
418 #define RK3568_VP_DSP_CTRL__DSP_LUT_EN BIT(28)
419 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20)
421 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17)
422 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16)
423 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15)
424 #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10)
425 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9)
426 #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8)
427 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7)
428 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6)
429 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5)
430 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4)
433 #define RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN BIT(22)
436 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)
438 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1)
439 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
442 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24)
444 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20)
450 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5)
451 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4)
452 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3)
453 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1)
454 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
463 #define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7)
464 #define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6)
465 #define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5)
466 #define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4)
467 #define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3)
468 #define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2)
469 #define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1)
470 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0)
489 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5)
490 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4)
492 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31)
494 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28)
500 #define VOP2_COLOR_KEY_MASK BIT(31)
502 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28)
503 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp)
528 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0)
530 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0)
537 #define VP_INT_DSP_HOLD_VALID BIT(6)
538 #define VP_INT_FS_FIELD BIT(5)
539 #define VP_INT_POST_BUF_EMPTY BIT(4)
540 #define VP_INT_LINE_FLAG1 BIT(3)
541 #define VP_INT_LINE_FLAG0 BIT(2)
542 #define VOP2_INT_BUS_ERRPR BIT(1)
543 #define VP_INT_FS BIT(0)
545 #define POLFLAG_DCLK_INV BIT(3)
558 ROCKCHIP_VOP2_PHY_ID_INVALID = -1,