Lines Matching full:vop2
36 #include <dt-bindings/soc/rockchip,vop2.h>
43 * VOP2 architecture
142 struct vop2 *vop2; member
160 struct vop2 *vop2; member
178 struct vop2 { struct
199 /* physical map length of vop2 register */ argument
285 static void vop2_lock(struct vop2 *vop2) in vop2_lock() argument
287 mutex_lock(&vop2->vop2_lock); in vop2_lock()
290 static void vop2_unlock(struct vop2 *vop2) in vop2_unlock() argument
292 mutex_unlock(&vop2->vop2_lock); in vop2_unlock()
295 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) in vop2_writel() argument
297 regmap_write(vop2->map, offset, v); in vop2_writel()
302 regmap_write(vp->vop2->map, vp->data->offset + offset, v); in vop2_vp_write()
305 static u32 vop2_readl(struct vop2 *vop2, u32 offset) in vop2_readl() argument
309 regmap_read(vop2->map, offset, &val); in vop2_readl()
318 regmap_read(vp->vop2->map, vp->data->offset + offset, &val); in vop2_vp_read()
344 struct vop2 *vop2 = vp->vop2; in vop2_cfg_done() local
349 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val); in vop2_cfg_done()
540 static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format) in vop2_output_rg_swap() argument
542 if (vop2->data->soc_id == 3588) { in vop2_output_rg_swap()
590 struct vop2 *vop2 = win->vop2; in rockchip_vop2_mod_supported() local
595 if (vop2->data->soc_id == 3568 || vop2->data->soc_id == 3566) { in rockchip_vop2_mod_supported()
598 drm_dbg_kms(vop2->drm, in rockchip_vop2_mod_supported()
606 if (vop2->data->soc_id == 3588) { in rockchip_vop2_mod_supported()
608 drm_dbg_kms(vop2->drm, "Only support 32 bpp format with afbc\n"); in rockchip_vop2_mod_supported()
618 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n", in rockchip_vop2_mod_supported()
763 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, in vop2_setup_scale() argument
805 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", in vop2_setup_scale()
947 struct vop2 *vop2 = vp->vop2; in vop2_crtc_enable_irq() local
949 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); in vop2_crtc_enable_irq()
950 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); in vop2_crtc_enable_irq()
955 struct vop2 *vop2 = vp->vop2; in vop2_crtc_disable_irq() local
957 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); in vop2_crtc_disable_irq()
960 static int vop2_core_clks_prepare_enable(struct vop2 *vop2) in vop2_core_clks_prepare_enable() argument
964 ret = clk_prepare_enable(vop2->hclk); in vop2_core_clks_prepare_enable()
966 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); in vop2_core_clks_prepare_enable()
970 ret = clk_prepare_enable(vop2->aclk); in vop2_core_clks_prepare_enable()
972 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); in vop2_core_clks_prepare_enable()
976 ret = clk_prepare_enable(vop2->pclk); in vop2_core_clks_prepare_enable()
978 drm_err(vop2->drm, "failed to enable pclk - %d\n", ret); in vop2_core_clks_prepare_enable()
984 clk_disable_unprepare(vop2->aclk); in vop2_core_clks_prepare_enable()
986 clk_disable_unprepare(vop2->hclk); in vop2_core_clks_prepare_enable()
991 static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2) in rk3588_vop2_power_domain_enable_all() argument
995 pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL); in rk3588_vop2_power_domain_enable_all()
999 vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd); in rk3588_vop2_power_domain_enable_all()
1002 static void vop2_enable(struct vop2 *vop2) in vop2_enable() argument
1006 ret = pm_runtime_resume_and_get(vop2->dev); in vop2_enable()
1008 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); in vop2_enable()
1012 ret = vop2_core_clks_prepare_enable(vop2); in vop2_enable()
1014 pm_runtime_put_sync(vop2->dev); in vop2_enable()
1018 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); in vop2_enable()
1020 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); in vop2_enable()
1024 if (vop2->data->soc_id == 3566) in vop2_enable()
1025 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); in vop2_enable()
1027 if (vop2->data->soc_id == 3588) in vop2_enable()
1028 rk3588_vop2_power_domain_enable_all(vop2); in vop2_enable()
1030 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); in vop2_enable()
1036 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, in vop2_enable()
1039 vop2_writel(vop2, RK3568_SYS0_INT_CLR, in vop2_enable()
1041 vop2_writel(vop2, RK3568_SYS0_INT_EN, in vop2_enable()
1043 vop2_writel(vop2, RK3568_SYS1_INT_CLR, in vop2_enable()
1045 vop2_writel(vop2, RK3568_SYS1_INT_EN, in vop2_enable()
1049 static void vop2_disable(struct vop2 *vop2) in vop2_disable() argument
1051 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); in vop2_disable()
1053 pm_runtime_put_sync(vop2->dev); in vop2_disable()
1055 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); in vop2_disable()
1057 clk_disable_unprepare(vop2->pclk); in vop2_disable()
1058 clk_disable_unprepare(vop2->aclk); in vop2_disable()
1059 clk_disable_unprepare(vop2->hclk); in vop2_disable()
1083 drm_err(vp->vop2->drm, "display LUT RAM enable timeout!\n"); in vop2_vp_dsp_lut_poll_disabled()
1106 static inline bool vop2_supports_seamless_gamma_lut_update(struct vop2 *vop2) in vop2_supports_seamless_gamma_lut_update() argument
1108 return (vop2->data->soc_id != 3566 && vop2->data->soc_id != 3568); in vop2_supports_seamless_gamma_lut_update()
1111 static bool vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp) in vop2_gamma_lut_in_use() argument
1113 const int nr_vps = vop2->data->nr_vps; in vop2_gamma_lut_in_use()
1117 if (vop2_vp_dsp_lut_is_enabled(&vop2->vps[gamma_en_vp_id])) in vop2_gamma_lut_in_use()
1127 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_disable() local
1131 vop2_lock(vop2); in vop2_crtc_atomic_disable()
1154 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); in vop2_crtc_atomic_disable()
1160 vop2->enable_count--; in vop2_crtc_atomic_disable()
1162 if (!vop2->enable_count) in vop2_crtc_atomic_disable()
1163 vop2_disable(vop2); in vop2_crtc_atomic_disable()
1165 vop2_unlock(vop2); in vop2_crtc_atomic_disable()
1184 struct vop2 *vop2; in vop2_plane_atomic_check() local
1197 vop2 = vp->vop2; in vop2_plane_atomic_check()
1198 vop2_data = vop2->data; in vop2_plane_atomic_check()
1219 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", in vop2_plane_atomic_check()
1228 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", in vop2_plane_atomic_check()
1241 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); in vop2_plane_atomic_check()
1253 struct vop2 *vop2 = win->vop2; in vop2_plane_atomic_disable() local
1255 drm_dbg(vop2->drm, "%s disable\n", win->data->name); in vop2_plane_atomic_disable()
1324 struct vop2 *vop2 = win->vop2; in vop2_plane_atomic_update() local
1350 * can't update plane when vop2 is disabled. in vop2_plane_atomic_update()
1396 drm_dbg_kms(vop2->drm, in vop2_plane_atomic_update()
1408 drm_dbg_kms(vop2->drm, in vop2_plane_atomic_update()
1423 drm_dbg_kms(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", in vop2_plane_atomic_update()
1430 drm_dbg_kms(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", in vop2_plane_atomic_update()
1441 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", in vop2_plane_atomic_update()
1447 if (vop2->data->soc_id > 3568) { in vop2_plane_atomic_update()
1476 drm_dbg_kms(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", in vop2_plane_atomic_update()
1507 if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) in vop2_plane_atomic_update()
1560 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); in vop2_plane_atomic_update()
1624 static void vop2_crtc_write_gamma_lut(struct vop2 *vop2, struct drm_crtc *crtc) in vop2_crtc_write_gamma_lut() argument
1627 const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id]; in vop2_crtc_write_gamma_lut()
1637 writel(word, vop2->lut_regs + i * 4); in vop2_crtc_write_gamma_lut()
1641 static void vop2_crtc_atomic_set_gamma_seamless(struct vop2 *vop2, in vop2_crtc_atomic_set_gamma_seamless() argument
1645 vop2_writel(vop2, RK3568_LUT_PORT_SEL, in vop2_crtc_atomic_set_gamma_seamless()
1648 vop2_crtc_write_gamma_lut(vop2, crtc); in vop2_crtc_atomic_set_gamma_seamless()
1652 static void vop2_crtc_atomic_set_gamma_rk356x(struct vop2 *vop2, in vop2_crtc_atomic_set_gamma_rk356x() argument
1661 vop2_writel(vop2, RK3568_LUT_PORT_SEL, vp->id); in vop2_crtc_atomic_set_gamma_rk356x()
1662 vop2_crtc_write_gamma_lut(vop2, crtc); in vop2_crtc_atomic_set_gamma_rk356x()
1666 static void vop2_crtc_atomic_try_set_gamma(struct vop2 *vop2, in vop2_crtc_atomic_try_set_gamma() argument
1671 if (!vop2->lut_regs) in vop2_crtc_atomic_try_set_gamma()
1679 if (vop2_supports_seamless_gamma_lut_update(vop2)) in vop2_crtc_atomic_try_set_gamma()
1680 vop2_crtc_atomic_set_gamma_seamless(vop2, vp, crtc); in vop2_crtc_atomic_try_set_gamma()
1682 vop2_crtc_atomic_set_gamma_rk356x(vop2, vp, crtc); in vop2_crtc_atomic_try_set_gamma()
1685 static inline void vop2_crtc_atomic_try_set_gamma_locked(struct vop2 *vop2, in vop2_crtc_atomic_try_set_gamma_locked() argument
1690 vop2_lock(vop2); in vop2_crtc_atomic_try_set_gamma_locked()
1691 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); in vop2_crtc_atomic_try_set_gamma_locked()
1692 vop2_unlock(vop2); in vop2_crtc_atomic_try_set_gamma_locked()
1744 vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id), in vop2_post_config()
1786 struct vop2 *vop2 = vp->vop2; in rk3568_set_intf_mux() local
1790 die = vop2_readl(vop2, RK3568_DSP_IF_EN); in rk3568_set_intf_mux()
1791 dip = vop2_readl(vop2, RK3568_DSP_IF_POL); in rk3568_set_intf_mux()
1801 regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); in rk3568_set_intf_mux()
1803 regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); in rk3568_set_intf_mux()
1848 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); in rk3568_set_intf_mux()
1854 vop2_writel(vop2, RK3568_DSP_IF_EN, die); in rk3568_set_intf_mux()
1855 vop2_writel(vop2, RK3568_DSP_IF_POL, dip); in rk3568_set_intf_mux()
1886 struct vop2 *vop2 = vp->vop2; in rk3588_calc_cru_cfg() local
1936 drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n", in rk3588_calc_cru_cfg()
1953 drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n", in rk3588_calc_cru_cfg()
1972 drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n", in rk3588_calc_cru_cfg()
2006 struct vop2 *vop2 = vp->vop2; in rk3588_set_intf_mux() local
2019 die = vop2_readl(vop2, RK3568_DSP_IF_EN); in rk3588_set_intf_mux()
2020 dip = vop2_readl(vop2, RK3568_DSP_IF_POL); in rk3588_set_intf_mux()
2021 div = vop2_readl(vop2, RK3568_DSP_IF_CTRL); in rk3588_set_intf_mux()
2033 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1)); in rk3588_set_intf_mux()
2034 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5)); in rk3588_set_intf_mux()
2045 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4)); in rk3588_set_intf_mux()
2046 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7)); in rk3588_set_intf_mux()
2056 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0)); in rk3588_set_intf_mux()
2066 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3)); in rk3588_set_intf_mux()
2099 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); in rk3588_set_intf_mux()
2106 vop2_writel(vop2, RK3568_DSP_IF_EN, die); in rk3588_set_intf_mux()
2107 vop2_writel(vop2, RK3568_DSP_IF_CTRL, div); in rk3588_set_intf_mux()
2108 vop2_writel(vop2, RK3568_DSP_IF_POL, dip); in rk3588_set_intf_mux()
2115 struct vop2 *vop2 = vp->vop2; in vop2_set_intf_mux() local
2117 if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) in vop2_set_intf_mux()
2119 else if (vop2->data->soc_id == 3588) in vop2_set_intf_mux()
2134 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_enable() local
2135 const struct vop2_data *vop2_data = vop2->data; in vop2_crtc_atomic_enable()
2158 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", in vop2_crtc_atomic_enable()
2162 vop2_lock(vop2); in vop2_crtc_atomic_enable()
2166 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", in vop2_crtc_atomic_enable()
2168 vop2_unlock(vop2); in vop2_crtc_atomic_enable()
2172 if (!vop2->enable_count) in vop2_crtc_atomic_enable()
2173 vop2_enable(vop2); in vop2_crtc_atomic_enable()
2175 vop2->enable_count++; in vop2_crtc_atomic_enable()
2201 vop2_unlock(vop2); in vop2_crtc_atomic_enable()
2215 if (vop2_output_rg_swap(vop2, vcstate->bus_format)) in vop2_crtc_atomic_enable()
2250 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), in vop2_crtc_atomic_enable()
2270 vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state); in vop2_crtc_atomic_enable()
2274 vop2_unlock(vop2); in vop2_crtc_atomic_enable()
2282 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_check_gamma() local
2285 if (!vp->vop2->lut_regs || !crtc_state->color_mgmt_changed || in vop2_crtc_atomic_check_gamma()
2291 drm_dbg(vop2->drm, "Invalid LUT size; got %d, expected %d\n", in vop2_crtc_atomic_check_gamma()
2296 if (!vop2_supports_seamless_gamma_lut_update(vop2) && vop2_gamma_lut_in_use(vop2, vp)) { in vop2_crtc_atomic_check_gamma()
2297 drm_info(vop2->drm, "Gamma LUT can be enabled for only one CRTC at a time\n"); in vop2_crtc_atomic_check_gamma()
2390 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) in vop2_find_start_mixer_id_for_vp() argument
2397 vp = &vop2->vps[i]; in vop2_find_start_mixer_id_for_vp()
2404 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) in vop2_setup_cluster_alpha() argument
2448 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, in vop2_setup_cluster_alpha()
2450 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, in vop2_setup_cluster_alpha()
2452 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, in vop2_setup_cluster_alpha()
2454 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, in vop2_setup_cluster_alpha()
2460 struct vop2 *vop2 = vp->vop2; in vop2_setup_alpha() local
2472 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); in vop2_setup_alpha()
2537 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, in vop2_setup_alpha()
2539 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, in vop2_setup_alpha()
2541 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, in vop2_setup_alpha()
2543 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, in vop2_setup_alpha()
2557 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, in vop2_setup_alpha()
2559 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, in vop2_setup_alpha()
2561 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, in vop2_setup_alpha()
2563 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, in vop2_setup_alpha()
2566 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); in vop2_setup_alpha()
2573 struct vop2 *vop2 = vp->vop2; in vop2_setup_layer_mixer() local
2583 struct vop2_video_port *vp0 = &vop2->vps[0]; in vop2_setup_layer_mixer()
2584 struct vop2_video_port *vp1 = &vop2->vps[1]; in vop2_setup_layer_mixer()
2585 struct vop2_video_port *vp2 = &vop2->vps[2]; in vop2_setup_layer_mixer()
2588 ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL); in vop2_setup_layer_mixer()
2595 vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); in vop2_setup_layer_mixer()
2597 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); in vop2_setup_layer_mixer()
2618 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); in vop2_setup_layer_mixer()
2622 ofs += vop2->vps[i].nlayers; in vop2_setup_layer_mixer()
2633 for (old_layer_id = 0; old_layer_id < vop2->data->win_size; old_layer_id++) { in vop2_setup_layer_mixer()
2642 for (i = 0; i < vop2->data->win_size; i++) { in vop2_setup_layer_mixer()
2643 old_win = &vop2->win[i]; in vop2_setup_layer_mixer()
2702 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); in vop2_setup_layer_mixer()
2703 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); in vop2_setup_layer_mixer()
2706 static void vop2_setup_dly_for_windows(struct vop2 *vop2) in vop2_setup_dly_for_windows() argument
2712 for (i = 0; i < vop2->data->win_size; i++) { in vop2_setup_dly_for_windows()
2715 win = &vop2->win[i]; in vop2_setup_dly_for_windows()
2744 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly); in vop2_setup_dly_for_windows()
2745 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); in vop2_setup_dly_for_windows()
2752 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_begin() local
2765 vop2_setup_cluster_alpha(vop2, win); in vop2_crtc_atomic_begin()
2773 vop2_setup_dly_for_windows(vop2); in vop2_crtc_atomic_begin()
2781 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_flush() local
2785 vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state); in vop2_crtc_atomic_flush()
2937 static void vop2_regs_print(struct vop2 *vop2, struct seq_file *s, in vop2_regs_print() argument
2945 val = vop2_readl(vop2, dump->base + dump->en_reg); in vop2_regs_print()
2952 start = vop2->res->start + dump->base; in vop2_regs_print()
2955 vop2_readl(vop2, dump->base + (4 * i)), in vop2_regs_print()
2956 vop2_readl(vop2, dump->base + (4 * (i + 1))), in vop2_regs_print()
2957 vop2_readl(vop2, dump->base + (4 * (i + 2))), in vop2_regs_print()
2958 vop2_readl(vop2, dump->base + (4 * (i + 3)))); in vop2_regs_print()
2965 struct vop2 *vop2 = node->info_ent->data; in __vop2_regs_dump() local
2973 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register); in __vop2_regs_dump()
2975 if (vop2->enable_count) { in __vop2_regs_dump()
2976 for (i = 0; i < vop2->data->regs_dump_size; i++) { in __vop2_regs_dump()
2977 dump = &vop2->data->regs_dump[i]; in __vop2_regs_dump()
2978 vop2_regs_print(vop2, s, dump, active_only); in __vop2_regs_dump()
3006 static void vop2_debugfs_init(struct vop2 *vop2, struct drm_minor *minor) in vop2_debugfs_init() argument
3011 root = debugfs_create_dir("vop2", minor->debugfs_root); in vop2_debugfs_init()
3014 vop2_debugfs_list[i].data = vop2; in vop2_debugfs_init()
3025 struct vop2 *vop2 = vp->vop2; in vop2_crtc_late_register() local
3028 vop2_debugfs_init(vop2, crtc->dev->primary); in vop2_crtc_late_register()
3087 struct vop2 *vop2 = data; in vop2_isr() local
3088 const struct vop2_data *vop2_data = vop2->data; in vop2_isr()
3095 * vop2-device is disabled the irq has to be targeted at the iommu. in vop2_isr()
3097 if (!pm_runtime_get_if_in_use(vop2->dev)) in vop2_isr()
3101 struct vop2_video_port *vp = &vop2->vps[i]; in vop2_isr()
3105 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); in vop2_isr()
3106 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); in vop2_isr()
3117 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); in vop2_isr()
3131 drm_err_ratelimited(vop2->drm, in vop2_isr()
3138 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); in vop2_isr()
3139 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); in vop2_isr()
3140 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); in vop2_isr()
3141 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); in vop2_isr()
3145 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); in vop2_isr()
3150 pm_runtime_put(vop2->dev); in vop2_isr()
3155 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, in vop2_plane_init() argument
3164 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, in vop2_plane_init()
3170 drm_err(vop2->drm, "failed to initialize plane %d\n", ret); in vop2_plane_init()
3183 vop2->registered_num_wins - 1); in vop2_plane_init()
3188 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) in find_vp_without_primary() argument
3192 for (i = 0; i < vop2->data->nr_vps; i++) { in find_vp_without_primary()
3193 struct vop2_video_port *vp = &vop2->vps[i]; in find_vp_without_primary()
3206 static int vop2_create_crtcs(struct vop2 *vop2) in vop2_create_crtcs() argument
3208 const struct vop2_data *vop2_data = vop2->data; in vop2_create_crtcs()
3209 struct drm_device *drm = vop2->drm; in vop2_create_crtcs()
3210 struct device *dev = vop2->dev; in vop2_create_crtcs()
3223 vp = &vop2->vps[i]; in vop2_create_crtcs()
3224 vp->vop2 = vop2; in vop2_create_crtcs()
3229 vp->dclk = devm_clk_get(vop2->dev, dclk_name); in vop2_create_crtcs()
3231 drm_err(vop2->drm, "failed to get %s\n", dclk_name); in vop2_create_crtcs()
3237 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); in vop2_create_crtcs()
3244 drm_err(vop2->drm, "no port node found for video_port%d\n", i); in vop2_create_crtcs()
3253 for (i = 0; i < vop2->registered_num_wins; i++) { in vop2_create_crtcs()
3254 struct vop2_win *win = &vop2->win[i]; in vop2_create_crtcs()
3257 if (vop2->data->soc_id == 3566) { in vop2_create_crtcs()
3272 vp = find_vp_without_primary(vop2); in vop2_create_crtcs()
3286 ret = vop2_plane_init(vop2, win, possible_crtcs); in vop2_create_crtcs()
3288 drm_err(vop2->drm, "failed to init plane %s: %d\n", in vop2_create_crtcs()
3295 vp = &vop2->vps[i]; in vop2_create_crtcs()
3306 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); in vop2_create_crtcs()
3311 if (vop2->lut_regs) { in vop2_create_crtcs()
3321 * On the VOP2 it's very hard to change the number of layers on a VP in vop2_create_crtcs()
3325 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_create_crtcs()
3326 struct vop2_video_port *vp = &vop2->vps[i]; in vop2_create_crtcs()
3335 static void vop2_destroy_crtcs(struct vop2 *vop2) in vop2_destroy_crtcs() argument
3337 struct drm_device *drm = vop2->drm; in vop2_destroy_crtcs()
3356 static int vop2_find_rgb_encoder(struct vop2 *vop2) in vop2_find_rgb_encoder() argument
3358 struct device_node *node = vop2->dev->of_node; in vop2_find_rgb_encoder()
3362 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_find_rgb_encoder()
3445 struct vop2 *vop2 = win->vop2; in vop2_cluster_init() local
3458 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, in vop2_cluster_init()
3533 struct vop2 *vop2 = win->vop2; in vop2_esmart_init() local
3546 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, in vop2_esmart_init()
3555 static int vop2_win_init(struct vop2 *vop2) in vop2_win_init() argument
3557 const struct vop2_data *vop2_data = vop2->data; in vop2_win_init()
3564 win = &vop2->win[i]; in vop2_win_init()
3569 win->vop2 = vop2; in vop2_win_init()
3578 vop2->registered_num_wins = vop2_data->win_size; in vop2_win_init()
3603 .name = "vop2",
3613 struct vop2 *vop2; in vop2_bind() local
3622 /* Allocate vop2 struct and its vop2_win array */ in vop2_bind()
3623 alloc_size = struct_size(vop2, win, vop2_data->win_size); in vop2_bind()
3624 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); in vop2_bind()
3625 if (!vop2) in vop2_bind()
3628 vop2->dev = dev; in vop2_bind()
3629 vop2->data = vop2_data; in vop2_bind()
3630 vop2->drm = drm; in vop2_bind()
3632 dev_set_drvdata(dev, vop2); in vop2_bind()
3636 drm_err(vop2->drm, "failed to get vop2 register byname\n"); in vop2_bind()
3640 vop2->res = res; in vop2_bind()
3641 vop2->regs = devm_ioremap_resource(dev, res); in vop2_bind()
3642 if (IS_ERR(vop2->regs)) in vop2_bind()
3643 return PTR_ERR(vop2->regs); in vop2_bind()
3644 vop2->len = resource_size(res); in vop2_bind()
3646 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); in vop2_bind()
3647 if (IS_ERR(vop2->map)) in vop2_bind()
3648 return PTR_ERR(vop2->map); in vop2_bind()
3650 ret = vop2_win_init(vop2); in vop2_bind()
3656 vop2->lut_regs = devm_ioremap_resource(dev, res); in vop2_bind()
3657 if (IS_ERR(vop2->lut_regs)) in vop2_bind()
3658 return PTR_ERR(vop2->lut_regs); in vop2_bind()
3661 vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); in vop2_bind()
3662 if (IS_ERR(vop2->sys_grf)) in vop2_bind()
3663 return dev_err_probe(dev, PTR_ERR(vop2->sys_grf), "cannot get sys_grf"); in vop2_bind()
3667 vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf"); in vop2_bind()
3668 if (IS_ERR(vop2->vop_grf)) in vop2_bind()
3669 return dev_err_probe(dev, PTR_ERR(vop2->vop_grf), "cannot get vop_grf"); in vop2_bind()
3673 vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf"); in vop2_bind()
3674 if (IS_ERR(vop2->vo1_grf)) in vop2_bind()
3675 return dev_err_probe(dev, PTR_ERR(vop2->vo1_grf), "cannot get vo1_grf"); in vop2_bind()
3679 vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); in vop2_bind()
3680 if (IS_ERR(vop2->sys_pmu)) in vop2_bind()
3681 return dev_err_probe(dev, PTR_ERR(vop2->sys_pmu), "cannot get sys_pmu"); in vop2_bind()
3684 vop2->hclk = devm_clk_get(vop2->dev, "hclk"); in vop2_bind()
3685 if (IS_ERR(vop2->hclk)) { in vop2_bind()
3686 drm_err(vop2->drm, "failed to get hclk source\n"); in vop2_bind()
3687 return PTR_ERR(vop2->hclk); in vop2_bind()
3690 vop2->aclk = devm_clk_get(vop2->dev, "aclk"); in vop2_bind()
3691 if (IS_ERR(vop2->aclk)) { in vop2_bind()
3692 drm_err(vop2->drm, "failed to get aclk source\n"); in vop2_bind()
3693 return PTR_ERR(vop2->aclk); in vop2_bind()
3696 vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); in vop2_bind()
3697 if (IS_ERR(vop2->pclk)) { in vop2_bind()
3698 drm_err(vop2->drm, "failed to get pclk source\n"); in vop2_bind()
3699 return PTR_ERR(vop2->pclk); in vop2_bind()
3702 vop2->irq = platform_get_irq(pdev, 0); in vop2_bind()
3703 if (vop2->irq < 0) { in vop2_bind()
3704 drm_err(vop2->drm, "cannot find irq for vop2\n"); in vop2_bind()
3705 return vop2->irq; in vop2_bind()
3708 mutex_init(&vop2->vop2_lock); in vop2_bind()
3710 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); in vop2_bind()
3714 ret = vop2_create_crtcs(vop2); in vop2_bind()
3718 ret = vop2_find_rgb_encoder(vop2); in vop2_bind()
3720 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc, in vop2_bind()
3721 vop2->drm, ret); in vop2_bind()
3722 if (IS_ERR(vop2->rgb)) { in vop2_bind()
3723 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) { in vop2_bind()
3724 ret = PTR_ERR(vop2->rgb); in vop2_bind()
3727 vop2->rgb = NULL; in vop2_bind()
3731 rockchip_drm_dma_init_device(vop2->drm, vop2->dev); in vop2_bind()
3738 vop2_destroy_crtcs(vop2); in vop2_bind()
3745 struct vop2 *vop2 = dev_get_drvdata(dev); in vop2_unbind() local
3749 if (vop2->rgb) in vop2_unbind()
3750 rockchip_rgb_fini(vop2->rgb); in vop2_unbind()
3752 vop2_destroy_crtcs(vop2); in vop2_unbind()