16 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on t…
17 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
67 #define FRAC_BITS 0xe
68 #define FRAC_MASK 0x3fff
87 	0x0007,
88 	0x003f,
89 	0x0263,
90 	0x0a24,
91 	0x2a6b,
92 	0x0a36,
93 	0x126d, /* H_TABLE_POS1 */
94 	0x1bfe,
95 	0x1a8f, /* H_TABLE_POS2 */
96 	0x1ec7,
97 	0x3863,
98 	0x1bfe,
99 	0x1bfe,
100 	0x1a2a,
101 	0x1e95,
102 	0x0e31,
103 	0x201b,
104 	0
108 	0x2001,
109 	0x200d,
110 	0x1006,
111 	0x0c06,
112 	0x1006,
113 	0x1818,
114 	0x21e3,
115 	0x1006,
116 	0x0c06,
117 	0x1006,
118 	0x1817,
119 	0x21d4,
120 	0x0002,
121 	0
125 	0x0007,
126 	0x0058,
127 	0x027c,
128 	0x0a31,
129 	0x2a77,
130 	0x0a95,
131 	0x124f, /* H_TABLE_POS1 */
132 	0x1bfe,
133 	0x1b22, /* H_TABLE_POS2 */
134 	0x1ef9,
135 	0x387c,
136 	0x1bfe,
137 	0x1bfe,
138 	0x1b31,
139 	0x1eb5,
140 	0x0e43,
141 	0x201b,
142 	0
146 	0x2001,
147 	0x200c,
148 	0x1005,
149 	0x0c05,
150 	0x1005,
151 	0x1401,
152 	0x1821,
153 	0x2240,
154 	0x1005,
155 	0x0c05,
156 	0x1005,
157 	0x1401,
158 	0x1822,
159 	0x2230,
160 	0x0002,
161 	0
259 			const_ptr = &available_tv_modes[0];  in radeon_legacy_tv_get_std_mode()
271 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
272 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
284 	WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);  in radeon_wait_pll_lock()
289 	for (i = 0; i < n_tests; i++) {  in radeon_wait_pll_lock()
290 		WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);  in radeon_wait_pll_lock()
291 		for (j = 0; j < n_wait_loops; j++)  in radeon_wait_pll_lock()
296 	WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);  in radeon_wait_pll_lock()
306 	int i = 0;  in radeon_legacy_tv_write_fifo()
315 		if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)  in radeon_legacy_tv_write_fifo()
319 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);  in radeon_legacy_tv_write_fifo()
322 #if 0 /* included for completeness */
328 	int i = 0;
335 		if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
339 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
349 	case 0:  in radeon_get_htiming_tables_addr()
359 		h_table = 0;  in radeon_get_htiming_tables_addr()
370 	case 0:  in radeon_get_vtiming_tables_addr()
380 		v_table = 0;  in radeon_get_vtiming_tables_addr()
399 	for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {  in radeon_restore_tv_timing_tables()
402 		if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)  in radeon_restore_tv_timing_tables()
405 	for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {  in radeon_restore_tv_timing_tables()
408 		if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)  in radeon_restore_tv_timing_tables()
571 		tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |  in radeon_legacy_tv_mode_set()
572 			(0x3b << RADEON_BLANK_LEVEL_SHIFT);  in radeon_legacy_tv_mode_set()
574 			((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);  in radeon_legacy_tv_mode_set()
577 		tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |  in radeon_legacy_tv_mode_set()
578 			((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);  in radeon_legacy_tv_mode_set()
581 			(0x3b << RADEON_SET_UP_LEVEL_SHIFT) |  in radeon_legacy_tv_mode_set()
582 			(0x3b << RADEON_BLANK_LEVEL_SHIFT);  in radeon_legacy_tv_mode_set()
590 		       | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)  in radeon_legacy_tv_mode_set()
591 		       | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)  in radeon_legacy_tv_mode_set()
592 		       | RADEON_RGB_ATTEN_SEL(0x3)  in radeon_legacy_tv_mode_set()
593 		       | RADEON_RGB_ATTEN_VAL(0xc));  in radeon_legacy_tv_mode_set()
613 	tmp &= 0xe3ff0000;  in radeon_legacy_tv_mode_set()
639 	for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {  in radeon_legacy_tv_mode_set()
654 	tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;  in radeon_legacy_tv_mode_set()
655 	tv_vscaler_cntl2 |= (0x10 << 24) |  in radeon_legacy_tv_mode_set()
663 	tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;  in radeon_legacy_tv_mode_set()
711 	tv_dac->tv.tv_uv_adr = 0xc8;  in radeon_legacy_tv_mode_set()
726 	for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {  in radeon_legacy_tv_mode_set()
728 		if (tv_dac->tv.h_code_timing[i] == 0)  in radeon_legacy_tv_mode_set()
732 	for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {  in radeon_legacy_tv_mode_set()
734 		if (tv_dac->tv.v_code_timing[i] == 0)  in radeon_legacy_tv_mode_set()
758 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);  in radeon_legacy_tv_mode_set()
764 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);  in radeon_legacy_tv_mode_set()
769 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);  in radeon_legacy_tv_mode_set()
773 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);  in radeon_legacy_tv_mode_set()
812 	WREG32(RADEON_TV_CRC_CNTL, 0);  in radeon_legacy_tv_mode_set()
816 	WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |  in radeon_legacy_tv_mode_set()
817 					       (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));  in radeon_legacy_tv_mode_set()
818 	WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |  in radeon_legacy_tv_mode_set()
819 						(0x100 << RADEON_Y_GAIN_SHIFT)));  in radeon_legacy_tv_mode_set()
859 	case 1: post_div = 0; break;  in get_post_div()
883 	*htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;  in radeon_legacy_tv_adjust_pll1()
887 	*ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);  in radeon_legacy_tv_adjust_pll1()
903 	*htotal2_cntl = (const_ptr->hor_total & 0x7);  in radeon_legacy_tv_adjust_pll2()
907 	*p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);  in radeon_legacy_tv_adjust_pll2()