Lines Matching +full:0 +full:x6800
32 #define R300_GA_POLY_MODE 0x4288
33 # define R300_FRONT_PTYPE_POINT (0 << 4)
36 # define R300_BACK_PTYPE_POINT (0 << 7)
39 #define R300_GA_ROUND_MODE 0x428c
40 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
41 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
42 # define R300_COLOR_ROUND_TRUNC (0 << 2)
44 #define R300_GB_MSPOS0 0x4010
45 # define R300_MS_X0_SHIFT 0
53 #define R300_GB_MSPOS1 0x4014
54 # define R300_MS_X3_SHIFT 0
62 #define R300_GA_ENHANCE 0x4274
63 # define R300_GA_DEADLOCK_CNTL (1 << 0)
65 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
66 # define R300_RB3D_DC_FLUSH (2 << 0)
69 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
70 # define R300_ZC_FLUSH (1 << 0)
72 # define R300_ZC_FLUSH_ALL 0x3
73 #define R400_GB_PIPE_SELECT 0x402c
74 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
75 #define R500_SU_REG_DEST 0x42c8
76 #define R300_GB_TILE_CONFIG 0x4018
77 # define R300_ENABLE_TILING (1 << 0)
78 # define R300_PIPE_COUNT_RV350 (0 << 1)
82 # define R300_TILE_SIZE_8 (0 << 4)
85 # define R300_SUBPIXEL_1_12 (0 << 16)
87 #define R300_DST_PIPE_CONFIG 0x170c
89 #define R300_RB2D_DSTCACHE_MODE 0x3428
93 #define RADEON_CP_STAT 0x7C0
94 #define RADEON_RBBM_CMDFIFO_ADDR 0xE70
95 #define RADEON_RBBM_CMDFIFO_DATA 0xE74
96 #define RADEON_ISYNC_CNTL 0x1724
97 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
104 #define RS480_NB_MC_INDEX 0x168
106 #define RS480_NB_MC_DATA 0x16c
111 #define RS690_MCCFG_FB_LOCATION 0x100
112 #define RS690_MC_FB_START_MASK 0x0000FFFF
113 #define RS690_MC_FB_START_SHIFT 0
114 #define RS690_MC_FB_TOP_MASK 0xFFFF0000
116 #define RS690_MCCFG_AGP_LOCATION 0x101
117 #define RS690_MC_AGP_START_MASK 0x0000FFFF
118 #define RS690_MC_AGP_START_SHIFT 0
119 #define RS690_MC_AGP_TOP_MASK 0xFFFF0000
121 #define RS690_MCCFG_AGP_BASE 0x102
122 #define RS690_MCCFG_AGP_BASE_2 0x103
123 #define RS690_MC_INIT_MISC_LAT_TIMER 0x104
124 #define RS690_HDP_FB_LOCATION 0x0134
125 #define RS690_MC_INDEX 0x78
126 # define RS690_MC_INDEX_MASK 0x1ff
128 # define RS690_MC_INDEX_WR_ACK 0x7f
129 #define RS690_MC_DATA 0x7c
130 #define RS690_MC_STATUS 0x90
131 #define RS690_MC_STATUS_IDLE (1 << 0)
132 #define RS480_AGP_BASE_2 0x0164
133 #define RS480_MC_MISC_CNTL 0x18
137 #define RS480_GART_FEATURE_ID 0x2b
142 # define RS480_2LEVEL_GART (0 << 30)
145 #define RS480_GART_BASE 0x2c
146 #define RS480_GART_CACHE_CNTRL 0x2e
147 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
148 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
149 # define RS480_GART_EN (1 << 0)
150 # define RS480_VA_SIZE_32MB (0 << 1)
157 #define RS480_AGP_MODE_CNTL 0x39
162 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
165 #define RS690_AIC_CTRL_SCRATCH 0x3A
171 #define RS600_MC_STATUS 0x0
172 #define RS600_MC_STATUS_IDLE (1 << 0)
173 #define RS600_MC_INDEX 0x70
174 # define RS600_MC_ADDR_MASK 0xffff
183 #define RS600_MC_DATA 0x74
184 #define RS600_MC_STATUS 0x0
186 #define RS600_MC_FB_LOCATION 0x4
187 #define RS600_MC_FB_START_MASK 0x0000FFFF
188 #define RS600_MC_FB_START_SHIFT 0
189 #define RS600_MC_FB_TOP_MASK 0xFFFF0000
191 #define RS600_MC_AGP_LOCATION 0x5
192 #define RS600_MC_AGP_START_MASK 0x0000FFFF
193 #define RS600_MC_AGP_START_SHIFT 0
194 #define RS600_MC_AGP_TOP_MASK 0xFFFF0000
196 #define RS600_MC_AGP_BASE 0x6
197 #define RS600_MC_AGP_BASE_2 0x7
198 #define RS600_MC_CNTL1 0x9
200 #define RS600_MC_PT0_CNTL 0x100
201 # define RS600_ENABLE_PT (1 << 0)
206 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102
207 # define RS600_ENABLE_PAGE_TABLE (1 << 0)
208 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
209 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
210 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
211 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
212 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
213 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
214 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
215 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c
216 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
219 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
223 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
236 #define RV515_MC_FB_LOCATION 0x01
237 #define RV515_MC_FB_START_MASK 0x0000FFFF
238 #define RV515_MC_FB_START_SHIFT 0
239 #define RV515_MC_FB_TOP_MASK 0xFFFF0000
241 #define RV515_MC_AGP_LOCATION 0x02
242 #define RV515_MC_AGP_START_MASK 0x0000FFFF
243 #define RV515_MC_AGP_START_SHIFT 0
244 #define RV515_MC_AGP_TOP_MASK 0xFFFF0000
246 #define RV515_MC_AGP_BASE 0x03
247 #define RV515_MC_AGP_BASE_2 0x04
249 #define R520_MC_FB_LOCATION 0x04
250 #define R520_MC_FB_START_MASK 0x0000FFFF
251 #define R520_MC_FB_START_SHIFT 0
252 #define R520_MC_FB_TOP_MASK 0xFFFF0000
254 #define R520_MC_AGP_LOCATION 0x05
255 #define R520_MC_AGP_START_MASK 0x0000FFFF
256 #define R520_MC_AGP_START_SHIFT 0
257 #define R520_MC_AGP_TOP_MASK 0xFFFF0000
259 #define R520_MC_AGP_BASE 0x06
260 #define R520_MC_AGP_BASE_2 0x07
263 #define AVIVO_MC_INDEX 0x0070
264 #define R520_MC_STATUS 0x00
266 #define RV515_MC_STATUS 0x08
268 #define RV515_MC_INIT_MISC_LAT_TIMER 0x09
269 #define AVIVO_MC_DATA 0x0074
271 #define R520_MC_IND_INDEX 0x70
273 #define R520_MC_IND_DATA 0x74
275 #define RV515_MC_CNTL 0x5
276 # define RV515_MEM_NUM_CHANNELS_MASK 0x3
277 #define R520_MC_CNTL0 0x8
278 # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)
282 #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
283 # define AVIVO_CP_FORCEON (1 << 0)
284 #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
285 # define AVIVO_E2_FORCEON (1 << 0)
286 #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
287 # define AVIVO_IDCT_FORCEON (1 << 0)
289 #define AVIVO_HDP_FB_LOCATION 0x134
291 #define AVIVO_VGA_RENDER_CONTROL 0x0300
293 #define AVIVO_D1VGA_CONTROL 0x0330
294 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
300 #define AVIVO_D2VGA_CONTROL 0x0338
302 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
303 #define AVIVO_EXT1_PPLL_REF_DIV 0x404
304 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
305 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
307 #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
308 #define AVIVO_EXT2_PPLL_REF_DIV 0x414
309 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
310 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
312 #define AVIVO_EXT1_PPLL_FB_DIV 0x430
313 #define AVIVO_EXT2_PPLL_FB_DIV 0x434
315 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
316 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c
318 #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
319 #define AVIVO_EXT2_PPLL_POST_DIV 0x444
321 #define AVIVO_EXT1_PPLL_CNTL 0x448
322 #define AVIVO_EXT2_PPLL_CNTL 0x44c
324 #define AVIVO_P1PLL_CNTL 0x450
325 #define AVIVO_P2PLL_CNTL 0x454
326 #define AVIVO_P1PLL_INT_SS_CNTL 0x458
327 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c
328 #define AVIVO_P1PLL_TMDSA_CNTL 0x460
329 #define AVIVO_P2PLL_LVTMA_CNTL 0x464
331 #define AVIVO_PCLK_CRTC1_CNTL 0x480
332 #define AVIVO_PCLK_CRTC2_CNTL 0x484
334 #define AVIVO_D1CRTC_H_TOTAL 0x6000
335 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
336 #define AVIVO_D1CRTC_H_SYNC_A 0x6008
337 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
338 #define AVIVO_D1CRTC_H_SYNC_B 0x6010
339 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
341 #define AVIVO_D1CRTC_V_TOTAL 0x6020
342 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
343 #define AVIVO_D1CRTC_V_SYNC_A 0x6028
344 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
345 #define AVIVO_D1CRTC_V_SYNC_B 0x6030
346 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
348 #define AVIVO_D1CRTC_CONTROL 0x6080
349 # define AVIVO_CRTC_EN (1 << 0)
351 #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
352 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
353 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
354 #define AVIVO_D1CRTC_STATUS 0x609c
355 # define AVIVO_D1CRTC_V_BLANK (1 << 0)
356 #define AVIVO_D1CRTC_STATUS_POSITION 0x60a0
357 #define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
358 #define AVIVO_D1CRTC_STATUS_HV_COUNT 0x60ac
359 #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
361 #define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
362 #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
363 #define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8
366 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8
367 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
369 #define AVIVO_D1GRPH_ENABLE 0x6100
370 #define AVIVO_D1GRPH_CONTROL 0x6104
371 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
372 # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
373 # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
374 # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
376 # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
378 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
384 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
390 # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
396 # define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
404 #define AVIVO_D1GRPH_LUT_SEL 0x6108
406 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
407 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
408 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
409 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
410 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
411 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
412 #define AVIVO_D1GRPH_PITCH 0x6120
413 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
414 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
415 #define AVIVO_D1GRPH_X_START 0x612c
416 #define AVIVO_D1GRPH_Y_START 0x6130
417 #define AVIVO_D1GRPH_X_END 0x6134
418 #define AVIVO_D1GRPH_Y_END 0x6138
419 #define AVIVO_D1GRPH_UPDATE 0x6144
422 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
423 # define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
425 #define AVIVO_D1CUR_CONTROL 0x6400
426 # define AVIVO_D1CURSOR_EN (1 << 0)
430 #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
431 #define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
432 #define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
433 #define AVIVO_D1CUR_SIZE 0x6410
434 #define AVIVO_D1CUR_POSITION 0x6414
435 #define AVIVO_D1CUR_HOT_SPOT 0x6418
436 #define AVIVO_D1CUR_UPDATE 0x6424
439 #define AVIVO_DC_LUT_RW_SELECT 0x6480
440 #define AVIVO_DC_LUT_RW_MODE 0x6484
441 #define AVIVO_DC_LUT_RW_INDEX 0x6488
442 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
443 #define AVIVO_DC_LUT_PWL_DATA 0x6490
444 #define AVIVO_DC_LUT_30_COLOR 0x6494
445 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
446 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
447 #define AVIVO_DC_LUT_AUTOFILL 0x64a0
449 #define AVIVO_DC_LUTA_CONTROL 0x64c0
450 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
451 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
452 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
453 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
454 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
455 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
457 #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
458 # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
459 # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
460 # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
466 # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
468 #define AVIVO_D1MODE_DATA_FORMAT 0x6528
469 # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
470 #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
471 #define AVIVO_D1MODE_VBLANK_STATUS 0x6534
473 #define AVIVO_D1MODE_VLINE_START_END 0x6538
474 #define AVIVO_D1MODE_VLINE_STATUS 0x653c
476 #define AVIVO_DxMODE_INT_MASK 0x6540
477 # define AVIVO_D1MODE_INT_MASK (1 << 0)
479 #define AVIVO_D1MODE_VIEWPORT_START 0x6580
480 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
481 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
482 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
484 #define AVIVO_D1SCL_SCALER_ENABLE 0x6590
485 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
486 #define AVIVO_D1SCL_UPDATE 0x65cc
490 #define AVIVO_D2CRTC_H_TOTAL 0x6800
491 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
492 #define AVIVO_D2CRTC_H_SYNC_A 0x6808
493 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
494 #define AVIVO_D2CRTC_H_SYNC_B 0x6810
495 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
497 #define AVIVO_D2CRTC_V_TOTAL 0x6820
498 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
499 #define AVIVO_D2CRTC_V_SYNC_A 0x6828
500 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
501 #define AVIVO_D2CRTC_V_SYNC_B 0x6830
502 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
504 #define AVIVO_D2CRTC_CONTROL 0x6880
505 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
506 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
507 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
508 #define AVIVO_D2CRTC_STATUS_POSITION 0x68a0
509 #define AVIVO_D2CRTC_FRAME_COUNT 0x68a4
510 #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
512 #define AVIVO_D2GRPH_ENABLE 0x6900
513 #define AVIVO_D2GRPH_CONTROL 0x6904
514 #define AVIVO_D2GRPH_LUT_SEL 0x6908
515 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
516 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
517 #define AVIVO_D2GRPH_PITCH 0x6920
518 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
519 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
520 #define AVIVO_D2GRPH_X_START 0x692c
521 #define AVIVO_D2GRPH_Y_START 0x6930
522 #define AVIVO_D2GRPH_X_END 0x6934
523 #define AVIVO_D2GRPH_Y_END 0x6938
524 #define AVIVO_D2GRPH_UPDATE 0x6944
525 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
527 #define AVIVO_D2CUR_CONTROL 0x6c00
528 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
529 #define AVIVO_D2CUR_SIZE 0x6c10
530 #define AVIVO_D2CUR_POSITION 0x6c14
532 #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
533 #define AVIVO_D2MODE_VLINE_START_END 0x6d38
534 #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c
535 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80
536 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
537 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
538 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
540 #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
541 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
543 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
545 #define AVIVO_DACA_ENABLE 0x7800
546 # define AVIVO_DAC_ENABLE (1 << 0)
547 #define AVIVO_DACA_SOURCE_SELECT 0x7804
548 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
549 # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
550 # define AVIVO_DAC_SOURCE_TV (2 << 0)
552 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
553 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
555 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
559 #define AVIVO_DACA_POWERDOWN 0x7850
560 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
565 #define AVIVO_DACB_ENABLE 0x7a00
566 #define AVIVO_DACB_SOURCE_SELECT 0x7a04
567 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
568 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
570 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
574 #define AVIVO_DACB_POWERDOWN 0x7a50
575 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
580 #define AVIVO_TMDSA_CNTL 0x7880
581 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
589 #define AVIVO_TMDSA_SOURCE_SELECT 0x7884
593 #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
594 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
602 #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
603 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
607 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
608 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
610 #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
611 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
612 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
625 #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
626 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
641 #define AVIVO_LVTMA_CNTL 0x7a80
642 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
650 #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
651 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
652 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
653 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
664 #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
665 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
670 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
671 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
673 #define R500_LVTMA_CLOCK_ENABLE 0x7b00
674 #define R600_LVTMA_CLOCK_ENABLE 0x7b04
676 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
677 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
690 #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
691 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
692 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
707 #define R500_LVTMA_PWRSEQ_CNTL 0x7af0
708 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4
709 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
723 #define R500_LVTMA_PWRSEQ_STATE 0x7af4
724 #define R600_LVTMA_PWRSEQ_STATE 0x7af8
725 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
732 #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
733 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
734 # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
737 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
739 #define AVIVO_DC_GPIO_HPD_A 0x7e94
740 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c
742 #define AVIVO_DC_I2C_STATUS1 0x7d30
743 # define AVIVO_DC_I2C_DONE (1 << 0)
747 #define AVIVO_DC_I2C_RESET 0x7d34
748 # define AVIVO_DC_I2C_SOFT_RESET (1 << 0)
750 #define AVIVO_DC_I2C_CONTROL1 0x7d38
751 # define AVIVO_DC_I2C_START (1 << 0)
756 # define AVIVO_SEL_DDC1 0
759 #define AVIVO_DC_I2C_CONTROL2 0x7d3c
760 # define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0)
762 #define AVIVO_DC_I2C_CONTROL3 0x7d40
763 # define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0)
769 #define AVIVO_DC_I2C_DATA 0x7d44
770 #define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48
771 # define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0)
774 #define AVIVO_DC_I2C_ARBITRATION 0x7d50
775 # define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0)
782 #define AVIVO_DC_GPIO_DDC1_MASK 0x7e40
783 #define AVIVO_DC_GPIO_DDC1_A 0x7e44
784 #define AVIVO_DC_GPIO_DDC1_EN 0x7e48
785 #define AVIVO_DC_GPIO_DDC1_Y 0x7e4c
787 #define AVIVO_DC_GPIO_DDC2_MASK 0x7e50
788 #define AVIVO_DC_GPIO_DDC2_A 0x7e54
789 #define AVIVO_DC_GPIO_DDC2_EN 0x7e58
790 #define AVIVO_DC_GPIO_DDC2_Y 0x7e5c
792 #define AVIVO_DC_GPIO_DDC3_MASK 0x7e60
793 #define AVIVO_DC_GPIO_DDC3_A 0x7e64
794 #define AVIVO_DC_GPIO_DDC3_EN 0x7e68
795 #define AVIVO_DC_GPIO_DDC3_Y 0x7e6c
797 #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc