2  * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
48 /* Atom needs data in little endian format so swap as appropriate when copying
90 	struct drm_device *dev = chan->dev;  in radeon_process_aux_ch()
91 	struct radeon_device *rdev = dev->dev_private;  in radeon_process_aux_ch()
100 	mutex_lock(&chan->mutex);  in radeon_process_aux_ch()
101 	mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);  in radeon_process_aux_ch()
103 	base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);  in radeon_process_aux_ch()
110 	args.v1.ucChannelID = chan->rec.i2c_id;  in radeon_process_aux_ch()
113 		args.v2.ucHPD_ID = chan->rec.hpd;  in radeon_process_aux_ch()
115 …atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof…  in radeon_process_aux_ch()
122 		r = -ETIMEDOUT;  in radeon_process_aux_ch()
129 		r = -EIO;  in radeon_process_aux_ch()
136 		r = -EIO;  in radeon_process_aux_ch()
149 	mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);  in radeon_process_aux_ch()
150 	mutex_unlock(&chan->mutex);  in radeon_process_aux_ch()
168 	if (WARN_ON(msg->size > 16))  in radeon_dp_aux_transfer_atom()
169 		return -E2BIG;  in radeon_dp_aux_transfer_atom()
171 	tx_buf[0] = msg->address & 0xff;  in radeon_dp_aux_transfer_atom()
172 	tx_buf[1] = (msg->address >> 8) & 0xff;  in radeon_dp_aux_transfer_atom()
173 	tx_buf[2] = (msg->request << 4) |  in radeon_dp_aux_transfer_atom()
174 		((msg->address >> 16) & 0xf);  in radeon_dp_aux_transfer_atom()
175 	tx_buf[3] = msg->size ? (msg->size - 1) : 0;  in radeon_dp_aux_transfer_atom()
177 	switch (msg->request & ~DP_AUX_I2C_MOT) {  in radeon_dp_aux_transfer_atom()
186 		if (WARN_ON_ONCE(msg->size > 12))  in radeon_dp_aux_transfer_atom()
187 			return -E2BIG;  in radeon_dp_aux_transfer_atom()
188 		/* tx_size needs to be 4 even for bare address packets since the atom  in radeon_dp_aux_transfer_atom()
189 		 * table needs the info in tx_buf[3].  in radeon_dp_aux_transfer_atom()
191 		tx_size = HEADER_SIZE + msg->size;  in radeon_dp_aux_transfer_atom()
192 		if (msg->size == 0)  in radeon_dp_aux_transfer_atom()
196 		memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);  in radeon_dp_aux_transfer_atom()
201 			ret = msg->size;  in radeon_dp_aux_transfer_atom()
205 		/* tx_size needs to be 4 even for bare address packets since the atom  in radeon_dp_aux_transfer_atom()
206 		 * table needs the info in tx_buf[3].  in radeon_dp_aux_transfer_atom()
209 		if (msg->size == 0)  in radeon_dp_aux_transfer_atom()
214 					    tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);  in radeon_dp_aux_transfer_atom()
217 		ret = -EINVAL;  in radeon_dp_aux_transfer_atom()
222 		msg->reply = ack >> 4;  in radeon_dp_aux_transfer_atom()
229 	struct drm_device *dev = radeon_connector->base.dev;  in radeon_dp_aux_init()
230 	struct radeon_device *rdev = dev->dev_private;  in radeon_dp_aux_init()
232 	radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;  in radeon_dp_aux_init()
233 	radeon_connector->ddc_bus->aux.drm_dev = radeon_connector->base.dev;  in radeon_dp_aux_init()
236 			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;  in radeon_dp_aux_init()
238 			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;  in radeon_dp_aux_init()
240 		radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;  in radeon_dp_aux_init()
243 	drm_dp_aux_init(&radeon_connector->ddc_bus->aux);  in radeon_dp_aux_init()
244 	radeon_connector->ddc_bus->has_aux = true;  in radeon_dp_aux_init()
335 	return -EINVAL;  in radeon_dp_get_dp_link_config()
352 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));  in radeon_dp_encoder_service()
358 	struct drm_device *dev = radeon_connector->base.dev;  in radeon_dp_getsinktype()
359 	struct radeon_device *rdev = dev->dev_private;  in radeon_dp_getsinktype()
362 					 radeon_connector->ddc_bus->rec.i2c_id, 0);  in radeon_dp_getsinktype()
367 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;  in radeon_dp_probe_oui()
370 	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))  in radeon_dp_probe_oui()
373 	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)  in radeon_dp_probe_oui()
377 	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)  in radeon_dp_probe_oui()
384 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;  in radeon_dp_getdpcd()
388 	ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,  in radeon_dp_getdpcd()
391 		memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);  in radeon_dp_getdpcd()
393 		DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),  in radeon_dp_getdpcd()
394 			      dig_connector->dpcd);  in radeon_dp_getdpcd()
401 	dig_connector->dpcd[0] = 0;  in radeon_dp_getdpcd()
408 	struct drm_device *dev = encoder->dev;  in radeon_dp_get_panel_mode()
409 	struct radeon_device *rdev = dev->dev_private;  in radeon_dp_get_panel_mode()
418 	if (!radeon_connector->con_priv)  in radeon_dp_get_panel_mode()
423 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,  in radeon_dp_get_panel_mode()
433 	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {  in radeon_dp_get_panel_mode()
435 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,  in radeon_dp_get_panel_mode()
452 	if (!radeon_connector->con_priv)  in radeon_dp_set_link_config()
454 	dig_connector = radeon_connector->con_priv;  in radeon_dp_set_link_config()
456 	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||  in radeon_dp_set_link_config()
457 	    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {  in radeon_dp_set_link_config()
458 		ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,  in radeon_dp_set_link_config()
459 						   mode->clock,  in radeon_dp_set_link_config()
460 						   &dig_connector->dp_lane_count,  in radeon_dp_set_link_config()
461 						   &dig_connector->dp_clock);  in radeon_dp_set_link_config()
463 			dig_connector->dp_clock = 0;  in radeon_dp_set_link_config()
464 			dig_connector->dp_lane_count = 0;  in radeon_dp_set_link_config()
477 	if ((mode->clock > 340000) &&  in radeon_dp_mode_valid_helper()
481 	if (!radeon_connector->con_priv)  in radeon_dp_mode_valid_helper()
483 	dig_connector = radeon_connector->con_priv;  in radeon_dp_mode_valid_helper()
485 	ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,  in radeon_dp_mode_valid_helper()
486 					   mode->clock,  in radeon_dp_mode_valid_helper()
502 	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;  in radeon_dp_needs_link_train()
504 	if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)  in radeon_dp_needs_link_train()
507 	if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))  in radeon_dp_needs_link_train()
518 	if (!radeon_connector->con_priv)  in radeon_dp_set_rx_power_state()
521 	dig_connector = radeon_connector->con_priv;  in radeon_dp_set_rx_power_state()
524 	if (dig_connector->dpcd[0] >= 0x11) {  in radeon_dp_set_rx_power_state()
525 		drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,  in radeon_dp_set_rx_power_state()
551 	atombios_dig_transmitter_setup(dp_info->encoder,  in radeon_dp_update_vs_emph()
553 				       0, dp_info->train_set[0]); /* sets all lanes at once */  in radeon_dp_update_vs_emph()
556 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,  in radeon_dp_update_vs_emph()
557 			  dp_info->train_set, dp_info->dp_lane_count);  in radeon_dp_update_vs_emph()
565 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {  in radeon_dp_set_tp()
577 		atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);  in radeon_dp_set_tp()
587 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,  in radeon_dp_set_tp()
588 					  dp_info->dp_clock, dp_info->enc_id, rtp);  in radeon_dp_set_tp()
592 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);  in radeon_dp_set_tp()
597 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);  in radeon_dp_link_train_init()
598 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;  in radeon_dp_link_train_init()
602 	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);  in radeon_dp_link_train_init()
605 	if (dp_info->dpcd[3] & 0x1)  in radeon_dp_link_train_init()
606 		drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
609 		drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
612 	if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)  in radeon_dp_link_train_init()
613 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);  in radeon_dp_link_train_init()
616 	tmp = dp_info->dp_lane_count;  in radeon_dp_link_train_init()
617 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in radeon_dp_link_train_init()
619 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);  in radeon_dp_link_train_init()
622 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);  in radeon_dp_link_train_init()
623 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);  in radeon_dp_link_train_init()
626 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)  in radeon_dp_link_train_init()
627 		atombios_dig_encoder_setup(dp_info->encoder,  in radeon_dp_link_train_init()
630 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,  in radeon_dp_link_train_init()
631 					  dp_info->dp_clock, dp_info->enc_id, 0);  in radeon_dp_link_train_init()
634 	drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
646 	drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_finish()
651 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)  in radeon_dp_link_train_finish()
652 		atombios_dig_encoder_setup(dp_info->encoder,  in radeon_dp_link_train_finish()
655 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,  in radeon_dp_link_train_finish()
656 					  dp_info->dp_clock, dp_info->enc_id, 0);  in radeon_dp_link_train_finish()
668 	memset(dp_info->train_set, 0, 4);  in radeon_dp_link_train_cr()
675 	dp_info->tries = 0;  in radeon_dp_link_train_cr()
678 		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);  in radeon_dp_link_train_cr()
680 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in radeon_dp_link_train_cr()
681 						 dp_info->link_status) <= 0) {  in radeon_dp_link_train_cr()
686 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in radeon_dp_link_train_cr()
691 		for (i = 0; i < dp_info->dp_lane_count; i++) {  in radeon_dp_link_train_cr()
692 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in radeon_dp_link_train_cr()
695 		if (i == dp_info->dp_lane_count) {  in radeon_dp_link_train_cr()
700 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in radeon_dp_link_train_cr()
701 			++dp_info->tries;  in radeon_dp_link_train_cr()
702 			if (dp_info->tries == 5) {  in radeon_dp_link_train_cr()
707 			dp_info->tries = 0;  in radeon_dp_link_train_cr()
709 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in radeon_dp_link_train_cr()
712 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);  in radeon_dp_link_train_cr()
718 		return -1;  in radeon_dp_link_train_cr()
720 		DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",  in radeon_dp_link_train_cr()
721 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in radeon_dp_link_train_cr()
722 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in radeon_dp_link_train_cr()
732 	if (dp_info->tp3_supported)  in radeon_dp_link_train_ce()
738 	dp_info->tries = 0;  in radeon_dp_link_train_ce()
741 		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);  in radeon_dp_link_train_ce()
743 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in radeon_dp_link_train_ce()
744 						 dp_info->link_status) <= 0) {  in radeon_dp_link_train_ce()
749 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in radeon_dp_link_train_ce()
755 		if (dp_info->tries > 5) {  in radeon_dp_link_train_ce()
761 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);  in radeon_dp_link_train_ce()
764 		dp_info->tries++;  in radeon_dp_link_train_ce()
769 		return -1;  in radeon_dp_link_train_ce()
771 		DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",  in radeon_dp_link_train_ce()
772 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in radeon_dp_link_train_ce()
773 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)  in radeon_dp_link_train_ce()
782 	struct drm_device *dev = encoder->dev;  in radeon_dp_link_train()
783 	struct radeon_device *rdev = dev->dev_private;  in radeon_dp_link_train()
792 	if (!radeon_encoder->enc_priv)  in radeon_dp_link_train()
794 	dig = radeon_encoder->enc_priv;  in radeon_dp_link_train()
797 	if (!radeon_connector->con_priv)  in radeon_dp_link_train()
799 	dig_connector = radeon_connector->con_priv;  in radeon_dp_link_train()
801 	if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&  in radeon_dp_link_train()
802 	    (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))  in radeon_dp_link_train()
811 	if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {  in radeon_dp_link_train()
817 	if (dig->dig_encoder)  in radeon_dp_link_train()
821 	if (dig->linkb)  in radeon_dp_link_train()
826 	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)  in radeon_dp_link_train()
836 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in radeon_dp_link_train()
840 	dp_info.dp_lane_count = dig_connector->dp_lane_count;  in radeon_dp_link_train()
841 	dp_info.dp_clock = dig_connector->dp_clock;  in radeon_dp_link_train()
842 	dp_info.aux = &radeon_connector->ddc_bus->aux;  in radeon_dp_link_train()