Lines Matching +full:2 +full:khz

60 #define ATOM_EXT_DAC          2
64 #define ATOM_CRTC3 2
75 #define ATOM_DCPLL 2
76 #define ATOM_PPLL0 2
86 #define ENCODER_REFCLK_SRC_DCPLL 2
95 #define ATOM_SCALER_EXPANSION 2
100 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
101 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
122 #define ATOM_TV_NTSCJ 2
132 #define ATOM_DAC1_CV 2
143 #define ATOM_PM_SUSPEND 2
155 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
181 #define HW_ASSISTED_I2C_STATUS_FAILURE 2
388 #define COMPUTE_ENGINE_PLL_PARAM 2
411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
444 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
445 ULONG ulClockFreq:24; // in unit of 10kHz
447 ULONG ulClockFreq:24; // in unit of 10kHz
448 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
474 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
513 ULONG ulReserved[2];
569 ULONG ulReserved[2];
584 ULONG ulTargetEngineClock; //In 10Khz unit
589 ULONG ulTargetEngineClock; //In 10Khz unit
598 ULONG ulTargetMemoryClock; //In 10Khz unit
603 ULONG ulTargetMemoryClock; //In 10Khz unit
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
639 UCHAR ucPadding[2];
668 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
676 USHORT usPixelClock; // in 10KHz; for bios convenient
692 USHORT usPixelClock; // in 10KHz; for bios convenient
694 // [2] Link Select:
706 // =2: DVI encoder
710 UCHAR ucReserved[2];
738 #define ATOM_ENCODER_MODE_DVI 2
746 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
747 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
752 UCHAR ucReserved1:2;
753 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
761 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
762 UCHAR ucReserved1:2;
769 USHORT usPixelClock; // in 10KHz; for bios convenient
775 // =2: DVI encoder
820 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
826 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
844 USHORT usPixelClock; // in 10KHz; for bios convenient
851 // =2: DVI encoder
873 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
874 UCHAR ucReserved:2;
875 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
877 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
878 UCHAR ucReserved:2;
879 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
900 USHORT usPixelClock; // in 10KHz; for bios convenient
910 // =2: DVI encoder
952 USHORT usPixelClock; // in 10KHz; for bios convenient
961 // [2] Link Select:
968 // =2: lane 8~11 or 8~15
1008 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
1021 // Following are used for DigTransmitterControlTable ver1.2
1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1026 // =1 Dig Transmitter 2 ( Uniphy CD )
1027 // =2 Dig Transmitter 3 ( Uniphy EF )
1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1045 // =1 Dig Transmitter 2 ( Uniphy CD )
1046 // =2 Dig Transmitter 3 ( Uniphy EF )
1080 USHORT usPixelClock; // in 10KHz; for bios convenient
1092 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1093 // =1 Dig Transmitter 2 ( Uniphy CD )
1094 // =2 Dig Transmitter 3 ( Uniphy EF )
1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1109 // =1 Dig Transmitter 2 ( Uniphy CD )
1110 // =2 Dig Transmitter 3 ( Uniphy EF )
1119 USHORT usPixelClock; // in 10KHz; for bios convenient
1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1175 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1188 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1189 // =1 Dig Transmitter 2 ( Uniphy CD )
1190 // =2 Dig Transmitter 3 ( Uniphy EF )
1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1205 // =1 Dig Transmitter 2 ( Uniphy CD )
1206 // =2 Dig Transmitter 3 ( Uniphy EF )
1214 USHORT usPixelClock; // in 10KHz; for bios convenient
1259 UCHAR ucPhyClkSrcId:2;
1265 UCHAR ucPhyClkSrcId:2;
1273 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= p…
1274 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1292 #define ATOM_PHY_ID_UNIPHYC 2
1310 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1331 // Bit3:2
1364 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1398 ULONG ulReserved[2];
1468 UCHAR ucPadding[2];
1505 UCHAR ucPadding[2];
1530 //#define ATOM_ENCODER_MODE_DVI 2
1544 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1556 //Major revision=1., Minor revision=2, add ucMiscIfno
1564 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1611 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1624 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1651 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1714 …DMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1730 UCHAR ucReserved[2];
1764 UCHAR ucReserved[2];
1767 // usDispPllConfig v1.2 for RoadRunner
1785 UCHAR ucReserved[2];
1804 UCHAR ucPadding[2];
1813 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1822 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1845 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
1855 //2bytesPS+offsetPS
1860 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1906 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1911 //ucTableFormatRevision=1,ucTableContentRevision=2
1940 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1965 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2002 ULONG ulTargetMemoryClock; //In 10Khz unit
2017 USHORT usPixelClock; // in 10KHz; for bios convenient
2035 //ucTableFormatRevision=1,ucTableContentRevision=2
2038 USHORT usPixelClock; // in 10KHz; for bios convenient
2054 // bit5=0: Gray level 2
2060 // =2: 50FRC_SEL pattern C
2090 UCHAR ucPadding[2];
2199 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2233 … usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2238 #define VOLTAGE_TYPE_MVDDC 2
2271 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2310 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2314 // New in GetVoltageInfo v1.2 ucVoltageMode
2330 USHORT usPixelClock; // in 10KHz; for bios convenient
2419 …UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM aud…
2420 …Info2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config…
2422 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2423 …UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical co…
2424 …UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical co…
2425 …UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical co…
2426 …UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical co…
2427 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2438 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2510 ULONG ulDefaultEngineClock; //In 10Khz unit
2511 ULONG ulDefaultMemoryClock; //In 10Khz unit
2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2517 ULONG ulASICMaxEngineClock; //In 10Khz unit
2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2522 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2523 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2524 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2525 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2526 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2527 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2528 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2529 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2530 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2531 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above…
2533 USHORT usReferenceClock; //In 10Khz unit
2544 ULONG ulDefaultEngineClock; //In 10Khz unit
2545 ULONG ulDefaultMemoryClock; //In 10Khz unit
2546 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2547 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2548 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2549 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2550 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2551 ULONG ulASICMaxEngineClock; //In 10Khz unit
2552 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2555 UCHAR ucPadding[2]; //Don't use them
2556 ULONG aulReservedForBIOS[2]; //Don't use them
2557 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2558 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2559 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2560 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2561 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2562 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2563 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2564 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2565 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2566 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2569 USHORT usReferenceClock; //In 10Khz unit
2580 ULONG ulDefaultEngineClock; //In 10Khz unit
2581 ULONG ulDefaultMemoryClock; //In 10Khz unit
2582 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2583 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2584 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2585 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2586 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2587 ULONG ulASICMaxEngineClock; //In 10Khz unit
2588 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2591 UCHAR ucPadding[2]; //Don't use them
2593 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2594 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2595 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2596 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2597 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2598 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2599 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2600 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2601 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2602 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2603 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2606 USHORT usReferenceClock; //In 10Khz unit
2617 ULONG ulDefaultEngineClock; //In 10Khz unit
2618 ULONG ulDefaultMemoryClock; //In 10Khz unit
2619 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2620 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2621 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2622 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2623 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2624 ULONG ulASICMaxEngineClock; //In 10Khz unit
2625 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2631 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2632 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2633 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2634 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2635 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2636 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2637 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2638 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2639 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2640 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2641 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2644 USHORT usReferenceClock; //In 10Khz unit
2656 ULONG ulDefaultEngineClock; //In 10Khz unit
2657 ULONG ulDefaultMemoryClock; //In 10Khz unit
2660 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2661 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2662 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2664 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2671 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2672 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2673 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2674 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2675 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2676 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2677 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2678 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2679 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2680 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2683 USHORT usCoreReferenceClock; //In 10Khz unit
2684 USHORT usMemoryReferenceClock; //In 10Khz unit
2685 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
2691 //ucTableFormatRevision=2
2692 //ucTableContentRevision=2
2697 ULONG ulDefaultEngineClock; //In 10Khz unit
2698 ULONG ulDefaultMemoryClock; //In 10Khz unit
2699 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2700 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2701 … ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2702 … ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2703 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2705 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
2712 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2717 …USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz uni…
2718 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2719 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2722 USHORT usCoreReferenceClock; //In 10Khz unit
2723 USHORT usMemoryReferenceClock; //In 10Khz unit
2724 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
2750 ULONG ulBootUpEngineClock; //in 10kHz unit
2751 ULONG ulBootUpMemoryClock; //in 10kHz unit
2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2759 ULONG ulReserved[2];
2763 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2771 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is re…
2822 ULONG ulBootUpEngineClock; //in 10kHz unit
2823 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2824 ULONG ulBootUpUMAClock; //in 10kHz unit
2825 ULONG ulBootUpSidePortClock; //in 10kHz unit
2826 ULONG ulMinSidePortClock; //in 10kHz unit
2833 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
2843 ULONG ulHTLinkFreq; //in 10Khz
2850 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2851 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2870 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2892 … the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1…
2896 …ith PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2917 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
2929 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2958 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
2995 ULONG ulBootUpEngineClock; //in 10kHz unit
2996 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
2997 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
2998 ULONG ulBootUpUMAClock; //in 10kHz unit
3016 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3060 #define ATOM_DP_ENCODER 2
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3177 // = 2, HW engine for Multimedia use
3310 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3376 USHORT usPixelClock; //in 10Khz unit
3437 //ucTableContentRevision=2
3458 UCHAR ucReserved[2];
3511 // Bit3:2: {Grey level}
3545 ULONG ulReserved[2];
3554 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
3611 #define LCD_MODE_CAP_CRTC_OFF 2
3629 #define LCD_RTS_RECORD_TYPE 2
3639 //ucTableContentRevision=2
3664 #define EXEC_SS_STEP_SIZE_SHIFT 2
3680 //ATOM_TV_NTSCJ 2
3699 #define MAX_SUPPORTED_TV_TIMING 2
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3838 if (FB_Size<=2Gb)
3972 //ucTableFormatRevision=2
4032 …USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encode…
4039 UCHAR ucPadding[2];
4072 #define EXT_HPDPIN_LUTINDEX_2 2
4082 #define EXT_AUXDDC_LUTINDEX_2 2
4092 … DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4093 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: fro…
4094 … DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4095 … DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4099 UCHAR ucDP_Lane3_Source:2;
4100 UCHAR ucDP_Lane2_Source:2;
4101 UCHAR ucDP_Lane1_Source:2;
4102 UCHAR ucDP_Lane0_Source:2;
4104 UCHAR ucDP_Lane0_Source:2;
4105 UCHAR ucDP_Lane1_Source:2;
4106 UCHAR ucDP_Lane2_Source:2;
4107 UCHAR ucDP_Lane3_Source:2;
4112 …I connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4113 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
4114 …I connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4115 …I connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4119 UCHAR ucDVI_CLK_Source:2;
4120 UCHAR ucDVI_DATA0_Source:2;
4121 UCHAR ucDVI_DATA1_Source:2;
4122 UCHAR ucDVI_DATA2_Source:2;
4124 UCHAR ucDVI_DATA2_Source:2;
4125 UCHAR ucDVI_DATA1_Source:2;
4126 UCHAR ucDVI_DATA0_Source:2;
4127 UCHAR ucDVI_CLK_Source:2;
4178 #define ATOM_HPD_INT_RECORD_TYPE 2
4280 UCHAR ucPadding[2];
4314 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
4327 UCHAR ucPadding[2];
4331 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW…
4332 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualifi…
4342 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4343 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4345 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4346 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4355 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
4386 UCHAR ucMuxState[2]; //for alligment purpose
4394 UCHAR ucMuxState[2]; //for alligment purpose
4434 #define CONNECTOR_TYPE_DVI_I 2
4626 UCHAR ucReserved[2];
4638 // 4:2 – load line slope trim.
4667 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
4673 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
4689 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
4693 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
4775 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4780 …upportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4864 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
4865 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4866 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
48952. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4906 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
4911 Bit[2]=0: DDR-PLL Power down feature disabled.
4924 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4931 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4962 ULONG uReserved:2;
4965 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
4967 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
4970 ULONG uReserved:2;
5079 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5080 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5081 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5097 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
51192. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5130 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5135 Bit[2]=0: DDR-PLL Power down feature disabled.
5150 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5157 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5209 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
5280 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5281 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5282 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5300 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5305 ulGPUCapInfo: bit[0~2]= Reserved
53202. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5335 Bit[2]=0: DDR-PLL Power down feature disabled.
5349 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
5357 …eed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
5370 … Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS op…
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5437 #define ICS91720 2
5472 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5474 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
5477 UCHAR ucReserved[2];
5483 #define ASIC_INTERNAL_ENGINE_SS 2
5497 … ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5503 UCHAR ucReserved[2];
5528 … ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5534 UCHAR ucReserved[2];
5552 #define ATOM_TV_STANDARD_DEF 2
5610 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
5651 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2
5883 #define ATOM_S6_LID_CHANGE_SHIFT 2
6004 ULONG ulTargetMemoryClock; //In 10Khz unit
6037 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2
6059 UCHAR ucSurface; // Surface 1 or 2
6067 UCHAR ucSurface; // Surface 1 or 2
6069 UCHAR ucPadding[2];
6076 UCHAR ucSurface; // Surface 1 or 2
6088 UCHAR ucSurface; // Surface 1 or 2
6140 #define PALETTE_DATA_READ 2
6154 #define HDP2_INTERRUPT_ID 2
6163 #define INTERRUPT_SERVICE_GET_STATUS 2
6167 #define INTERRUPT_STATUS__HPD_HIGH 2
6180 #define INDIRECT_IO_MC 2
6401 UCHAR ucRow; // Number of Row,in power of 2;
6402 UCHAR ucColumn; // Number of Column,in power of 2;
6404 UCHAR ucRank; // Number of Rank, in power of 2
6406 …elConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
6409 UCHAR ucReserved[2];
6428 UCHAR ucRow; // Number of Row,in power of 2;
6429 UCHAR ucColumn; // Number of Column,in power of 2;
6431 UCHAR ucRank; // Number of Rank, in power of 2
6433 …elConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
6443 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6479 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6512 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6559 UCHAR ucRow; // Number of Row,in power of 2;
6560 UCHAR ucColumn; // Number of Column,in power of 2;
6562 UCHAR ucRank; // Number of Rank, in power of 2
6627 UCHAR ucReserved2[2];
6714 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6757 …; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
6758 … // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... D…
6819 #define SW_I2C_IO_DRIVE 2
6831 #define SW_I2C_CNTL_START 2
7016 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
7076 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
7094 UCHAR ucReserved[2];
7105 CLOCK_SRC_XO_IN2=2,
7142 …UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
7160 UCHAR ucReserved[2];
7192 UCHAR ucReserved[2];
7266 #define ATOM_FEATURE_SUPPORTED 2
7278 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
7289 #define SELECT_DCIO_UNIPHY_LINK0 2
7382 #define GFX_HARVESTING_PRIM_ID 2
7414 USHORT usMaxFrequency; // in 10kHz unit
7452 // = 2 - DVI-I
7467 // = 2 - DACB
7545 USHORT usMaxFrequency; // in 10Khz
7586 #define ATOM_XTMDS_ASIC_SI178_ID 2
7610 UCHAR ucPadding[2];
7643 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7653 …OWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Bala…
7685 //ucTableFormatRevision=2
7700 //ucTableFormatRevision=2
7701 //ucTableContentRevision=2