Lines Matching full:word
95 #define GPU_SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
96 #define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
97 #define GPU_TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
98 #define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
100 #define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
101 #define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
107 #define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */
108 #define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
110 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
111 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
113 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
114 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
116 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
117 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
119 #define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */
120 #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */
123 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
124 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
126 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
127 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
129 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
130 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
132 #define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */
133 #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */
136 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
137 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
139 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
140 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
142 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
143 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
145 #define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */
146 #define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */
149 #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */
150 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
152 #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */
153 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
155 #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */
156 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
158 #define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */
159 #define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */
162 #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */
163 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
165 #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */
166 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
168 #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */
169 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
298 …LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */
299 …I(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
300 … AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */
301 …AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */
302 …S_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */
303 …_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
306 … AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */
307 …AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */
310 …O(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */
311 …(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
312 …TEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */
313 …EXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */