Lines Matching +full:high +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
16 #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */
26 #define GPU_IRQ_FAULT BIT(0)
27 #define GPU_IRQ_MULTIPLE_FAULT BIT(7)
28 #define GPU_IRQ_RESET_COMPLETED BIT(8)
29 #define GPU_IRQ_POWER_CHANGED BIT(9)
30 #define GPU_IRQ_POWER_CHANGED_ALL BIT(10)
31 #define GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16)
32 #define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
55 #define GPU_STATUS_PRFCNT_ACTIVE BIT(2)
96 #define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
98 #define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
101 #define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
104 #define COHERENCY_ACE_LITE BIT(0)
105 #define COHERENCY_ACE BIT(1)
108 #define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
111 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
114 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
117 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
120 #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */
124 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
127 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
130 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
133 #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */
137 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
140 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
143 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
146 #define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */
150 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
153 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
156 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
159 #define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */
163 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
166 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
169 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
198 #define SC_ALT_COUNTERS BIT(3)
199 #define SC_OVERRIDE_FWD_PIXEL_KILL BIT(4)
200 #define SC_SDC_DISABLE_OQ_DISCARD BIT(6)
201 #define SC_LS_ALLOW_ATTR_TYPES BIT(16)
202 #define SC_LS_PAUSEBUFFER_DISABLE BIT(16)
203 #define SC_TLS_HASH_ENABLE BIT(17)
204 #define SC_LS_ATTR_CHECK_DISABLE BIT(18)
205 #define SC_ENABLE_TEXGRD_FLAGS BIT(25)
206 #define SC_VAR_ALGORITHM BIT(29)
210 #define TC_CLOCK_GATE_OVERRIDE BIT(0)
213 #define JM_TIMESTAMP_OVERRIDE BIT(0)
214 #define JM_CLOCK_GATE_OVERRIDE BIT(1)
215 #define JM_JOB_THROTTLE_ENABLE BIT(2)
233 #define JOB_INT_MASK_ERR(j) BIT((j) + 16)
234 #define JOB_INT_MASK_DONE(j) BIT(j)
258 #define JS_CONFIG_START_FLUSH_CLEAN BIT(8)
260 #define JS_CONFIG_START_MMU BIT(10)
261 #define JS_CONFIG_JOB_CHAIN_FLAG BIT(11)
262 #define JS_CONFIG_END_FLUSH_CLEAN BIT(12)
264 #define JS_CONFIG_ENABLE_FLUSH_REDUCTION BIT(14)
265 #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK BIT(15)
289 (deprecated - only for use with T60x) */
299 …I(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
301 #define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high …
303 …_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
307 #define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high…
311 …(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
313 …EXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */
324 #define AS_TRANSTAB_LPAE_READ_INNER BIT(2)
325 #define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4)
337 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
338 #define gpu_read(dev, reg) readl(dev->iomem + reg)