40 	mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x5a, 0x5a)
42 	mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0xa5, 0xa5)
44 	mipi_dsi_dcs_write_seq_multi(ctx, 0xfc, 0x5a, 0x5a)
46 	mipi_dsi_dcs_write_seq_multi(ctx, 0xfc, 0xa5, 0xa5)
48 	mipi_dsi_dcs_write_seq_multi(ctx, 0x9f, 0xa5, 0xa5)
50 	mipi_dsi_dcs_write_seq_multi(ctx, 0x9f, 0x5a, 0x5a)
52 	mipi_dsi_dcs_write_seq_multi(ctx, 0xe2, 0x00, 0x00)
58 	gpiod_set_value_cansleep(priv->reset_gpio, 0);  in s6e3ha8_amb577px01_wqhd_reset()
81 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x13);  in s6e3ha8_amb577px01_wqhd_on()
86 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x13);  in s6e3ha8_amb577px01_wqhd_on()
91 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x07);  in s6e3ha8_amb577px01_wqhd_on()
93 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x3c, 0x10);  in s6e3ha8_amb577px01_wqhd_on()
94 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x0b);  in s6e3ha8_amb577px01_wqhd_on()
96 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x30);  in s6e3ha8_amb577px01_wqhd_on()
98 	mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x00, 0x00, 0x05, 0x9f); /* CASET */  in s6e3ha8_amb577px01_wqhd_on()
99 	mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x00, 0x00, 0x0b, 0x8f); /* PASET */  in s6e3ha8_amb577px01_wqhd_on()
100 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x01); /* scaler setup : scaler off */  in s6e3ha8_amb577px01_wqhd_on()
103 	mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x00); /* TE Vsync ON */  in s6e3ha8_amb577px01_wqhd_on()
106 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xed, 0x4c); /* ERR_FG */  in s6e3ha8_amb577px01_wqhd_on()
111 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xc5, 0x0d, 0x10, 0xb4, 0x3e, 0x01);  in s6e3ha8_amb577px01_wqhd_on()
115 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9,  in s6e3ha8_amb577px01_wqhd_on()
116 				   0x00, 0xb0, 0x81, 0x09, 0x00, 0x00, 0x00,  in s6e3ha8_amb577px01_wqhd_on()
117 				   0x11, 0x03); /* TSP HSYNC Setting */  in s6e3ha8_amb577px01_wqhd_on()
121 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x03);  in s6e3ha8_amb577px01_wqhd_on()
122 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf6, 0x43);  in s6e3ha8_amb577px01_wqhd_on()
127 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xca,  in s6e3ha8_amb577px01_wqhd_on()
128 				   0x07, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80,  in s6e3ha8_amb577px01_wqhd_on()
129 				   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,  in s6e3ha8_amb577px01_wqhd_on()
130 				   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,  in s6e3ha8_amb577px01_wqhd_on()
131 				   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,  in s6e3ha8_amb577px01_wqhd_on()
132 				   0x80, 0x80, 0x80, 0x00, 0x00, 0x00);  in s6e3ha8_amb577px01_wqhd_on()
133 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0x0c); /* AID Set : 0% */  in s6e3ha8_amb577px01_wqhd_on()
134 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5,  in s6e3ha8_amb577px01_wqhd_on()
135 				   0x19, 0xdc, 0x16, 0x01, 0x34, 0x67, 0x9a,  in s6e3ha8_amb577px01_wqhd_on()
136 				   0xcd, 0x01, 0x22, 0x33, 0x44, 0x00, 0x00,  in s6e3ha8_amb577px01_wqhd_on()
137 				   0x05, 0x55, 0xcc, 0x0c, 0x01, 0x11, 0x11,  in s6e3ha8_amb577px01_wqhd_on()
138 				   0x10); /* MPS/ELVSS Setting */  in s6e3ha8_amb577px01_wqhd_on()
139 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf4, 0xeb, 0x28); /* VINT */  in s6e3ha8_amb577px01_wqhd_on()
140 	mipi_dsi_dcs_write_seq_multi(&ctx, 0xf7, 0x03); /* Gamma, LTPS(AID) update */  in s6e3ha8_amb577px01_wqhd_on()
190 	if (ret < 0)  in s6e3ha8_amb577px01_wqhd_prepare()
196 	if (ret < 0) {  in s6e3ha8_amb577px01_wqhd_prepare()
263 	if (ret < 0) {  in s6e3ha8_amb577px01_wqhd_probe()
303 	if (ret < 0) {  in s6e3ha8_amb577px01_wqhd_probe()
309 	return 0;  in s6e3ha8_amb577px01_wqhd_probe()
318 	if (ret < 0)  in s6e3ha8_amb577px01_wqhd_remove()