21 #define MCS_ACCESS_PROT_OFF	0xb0
22 #define MCS_UNKNOWN_B7		0xb7
23 #define MCS_BIAS_CURRENT_CTRL	0xd1
24 #define MCS_PASSWD1		0xf0
25 #define MCS_PASSWD2		0xfc
26 #define MCS_UNKNOWN_FF		0xff
51 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in ams639rq08_reset()
61 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a);  in ams639rq08_on()
62 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0x5a, 0x5a);  in ams639rq08_on()
63 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x0c);  in ams639rq08_on()
64 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_UNKNOWN_FF, 0x10);  in ams639rq08_on()
65 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x2f);  in ams639rq08_on()
66 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_BIAS_CURRENT_CTRL, 0x01);  in ams639rq08_on()
67 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5);  in ams639rq08_on()
68 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0xa5, 0xa5);  in ams639rq08_on()
75 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a);  in ams639rq08_on()
80 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_UNKNOWN_B7, 0x01, 0x4b);  in ams639rq08_on()
83 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x06);  in ams639rq08_on()
84 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_UNKNOWN_B7, 0x10);  in ams639rq08_on()
85 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5);  in ams639rq08_on()
88 	mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x0923);  in ams639rq08_on()
90 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a);  in ams639rq08_on()
91 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0x5a, 0x5a);  in ams639rq08_on()
94 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x23);  in ams639rq08_on()
95 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_BIAS_CURRENT_CTRL, 0x11);  in ams639rq08_on()
98 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe9, 0x11, 0x55,  in ams639rq08_on()
99 					       0xa6, 0x75, 0xa3,  in ams639rq08_on()
100 					       0xb9, 0xa1, 0x4a,  in ams639rq08_on()
101 					       0x00, 0x1a, 0xb8);  in ams639rq08_on()
104 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1,  in ams639rq08_on()
105 					       0x00, 0x00, 0x02,  in ams639rq08_on()
106 					       0x02, 0x42, 0x02);  in ams639rq08_on()
107 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2,  in ams639rq08_on()
108 					       0x00, 0x00, 0x00,  in ams639rq08_on()
109 					       0x00, 0x00, 0x00);  in ams639rq08_on()
110 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x0c);  in ams639rq08_on()
111 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x19);  in ams639rq08_on()
112 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5);  in ams639rq08_on()
113 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0xa5, 0xa5);  in ams639rq08_on()
114 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);  in ams639rq08_on()
117 	mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x0000);  in ams639rq08_on()
120 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);  in ams639rq08_on()
145 	if (ret < 0)  in ams639rq08_prepare()
151 	if (ret < 0) {  in ams639rq08_prepare()
158 	return 0;  in ams639rq08_prepare()
171 	return 0;  in ams639rq08_unprepare()
210 	if (ret < 0)  in ams639rq08_bl_update_status()
215 	return 0;  in ams639rq08_bl_update_status()
227 	if (ret < 0)  in ams639rq08_bl_get_brightness()
268 	if (ret < 0)  in ams639rq08_probe()
296 	if (ret < 0) {  in ams639rq08_probe()
301 	return 0;  in ams639rq08_probe()