21 #define MCS_ACCESS_PROT_OFF	0xb0
22 #define MCS_PASSWD		0xf0
47 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in ams581vf01_reset()
64 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0x5a, 0x5a); /* Unlock */  in ams581vf01_on()
65 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xeb, 0x17,  in ams581vf01_on()
66 					       0x41, 0x92,  in ams581vf01_on()
67 					       0x0e, 0x10,  in ams581vf01_on()
68 					       0x82, 0x5a);  in ams581vf01_on()
69 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0xa5, 0xa5); /* Lock */  in ams581vf01_on()
72 	mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x0437);  in ams581vf01_on()
73 	mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x0923);  in ams581vf01_on()
76 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);  in ams581vf01_on()
79 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0x5a, 0x5a); /* Unlock */  in ams581vf01_on()
80 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x09);  in ams581vf01_on()
81 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe8, 0x11, 0x30);  in ams581vf01_on()
82 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0xa5, 0xa5); /* Lock */  in ams581vf01_on()
102 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0x5a, 0x5a); /* Unlock */  in ams581vf01_off()
103 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x05);  in ams581vf01_off()
104 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x01);  in ams581vf01_off()
105 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0xa5, 0xa5);  /* Lock */  in ams581vf01_off()
117 	if (ret < 0)  in ams581vf01_prepare()
123 	if (ret < 0) {  in ams581vf01_prepare()
130 	return 0;  in ams581vf01_prepare()
143 	return 0;  in ams581vf01_unprepare()
182 	if (ret < 0)  in ams581vf01_bl_update_status()
187 	return 0;  in ams581vf01_bl_update_status()
222 	if (ret < 0)  in ams581vf01_probe()
250 	if (ret < 0) {  in ams581vf01_probe()
255 	return 0;  in ams581vf01_probe()