26 #define MCS_ADRSFT	0x0000	/* Address Shift Function */
27 #define MCS_PANSET	0xB3A6	/* Panel Type Setting */
28 #define MCS_SD_CTRL	0xC0A2	/* Source Driver Timing Setting */
29 #define MCS_P_DRV_M	0xC0B4	/* Panel Driving Mode */
30 #define MCS_OSC_ADJ	0xC181	/* Oscillator Adjustment for Idle/Normal mode */
31 #define MCS_RGB_VID_SET	0xC1A1	/* RGB Video Mode Setting */
32 #define MCS_SD_PCH_CTRL	0xC480	/* Source Driver Precharge Control */
33 #define MCS_NO_DOC1	0xC48A	/* Command not documented */
34 #define MCS_PWR_CTRL1	0xC580	/* Power Control Setting 1 */
35 #define MCS_PWR_CTRL2	0xC590	/* Power Control Setting 2 for Normal Mode */
36 #define MCS_PWR_CTRL4	0xC5B0	/* Power Control Setting 4 for DC Voltage */
37 #define MCS_PANCTRLSET1	0xCB80	/* Panel Control Setting 1 */
38 #define MCS_PANCTRLSET2	0xCB90	/* Panel Control Setting 2 */
39 #define MCS_PANCTRLSET3	0xCBA0	/* Panel Control Setting 3 */
40 #define MCS_PANCTRLSET4	0xCBB0	/* Panel Control Setting 4 */
41 #define MCS_PANCTRLSET5	0xCBC0	/* Panel Control Setting 5 */
42 #define MCS_PANCTRLSET6	0xCBD0	/* Panel Control Setting 6 */
43 #define MCS_PANCTRLSET7	0xCBE0	/* Panel Control Setting 7 */
44 #define MCS_PANCTRLSET8	0xCBF0	/* Panel Control Setting 8 */
45 #define MCS_PANU2D1	0xCC80	/* Panel U2D Setting 1 */
46 #define MCS_PANU2D2	0xCC90	/* Panel U2D Setting 2 */
47 #define MCS_PANU2D3	0xCCA0	/* Panel U2D Setting 3 */
48 #define MCS_PAND2U1	0xCCB0	/* Panel D2U Setting 1 */
49 #define MCS_PAND2U2	0xCCC0	/* Panel D2U Setting 2 */
50 #define MCS_PAND2U3	0xCCD0	/* Panel D2U Setting 3 */
51 #define MCS_GOAVST	0xCE80	/* GOA VST Setting */
52 #define MCS_GOACLKA1	0xCEA0	/* GOA CLKA1 Setting */
53 #define MCS_GOACLKA3	0xCEB0	/* GOA CLKA3 Setting */
54 #define MCS_GOAECLK	0xCFC0	/* GOA ECLK Setting */
55 #define MCS_NO_DOC2	0xCFD0	/* Command not documented */
56 #define MCS_GVDDSET	0xD800	/* GVDD/NGVDD */
57 #define MCS_VCOMDC	0xD900	/* VCOM Voltage Setting */
58 #define MCS_GMCT2_2P	0xE100	/* Gamma Correction 2.2+ Setting */
59 #define MCS_GMCT2_2N	0xE200	/* Gamma Correction 2.2- Setting */
60 #define MCS_NO_DOC3	0xF5B6	/* Command not documented */
61 #define MCS_CMD2_ENA1	0xFF00	/* Enable Access Command2 "CMD2" */
62 #define MCS_CMD2_ENA2	0xFF80	/* Enable Access Orise Command2 */
117 	if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0)  in otm8009a_dcs_write_buf()
129 	dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF);	\
139 	dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);  in otm8009a_init_sequence()
142 	dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09);  in otm8009a_init_sequence()
144 	dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30);  in otm8009a_init_sequence()
147 	dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40);  in otm8009a_init_sequence()
150 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9);  in otm8009a_init_sequence()
151 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34);  in otm8009a_init_sequence()
152 	dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50);  in otm8009a_init_sequence()
153 	dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E);  in otm8009a_init_sequence()
154 	dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */  in otm8009a_init_sequence()
155 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01);  in otm8009a_init_sequence()
156 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34);  in otm8009a_init_sequence()
157 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33);  in otm8009a_init_sequence()
158 	dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79);  in otm8009a_init_sequence()
159 	dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B);  in otm8009a_init_sequence()
160 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83);  in otm8009a_init_sequence()
161 	dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83);  in otm8009a_init_sequence()
162 	dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E);  in otm8009a_init_sequence()
163 	dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01);  in otm8009a_init_sequence()
165 	dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);  in otm8009a_init_sequence()
166 	dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,  in otm8009a_init_sequence()
167 			 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);  in otm8009a_init_sequence()
168 	dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,  in otm8009a_init_sequence()
169 			 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);  in otm8009a_init_sequence()
170 	dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,  in otm8009a_init_sequence()
171 			 0x01, 0x02, 0x00, 0x00);  in otm8009a_init_sequence()
173 	dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00);  in otm8009a_init_sequence()
175 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);  in otm8009a_init_sequence()
176 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  in otm8009a_init_sequence()
177 			 0, 0, 0, 0, 0);  in otm8009a_init_sequence()
178 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  in otm8009a_init_sequence()
179 			 0, 0, 0, 0, 0);  in otm8009a_init_sequence()
180 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);  in otm8009a_init_sequence()
181 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,  in otm8009a_init_sequence()
182 			 0, 0, 0, 0, 0);  in otm8009a_init_sequence()
183 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,  in otm8009a_init_sequence()
184 			 4, 0, 0, 0, 0);  in otm8009a_init_sequence()
185 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);  in otm8009a_init_sequence()
186 	dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,  in otm8009a_init_sequence()
187 			 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);  in otm8009a_init_sequence()
189 	dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,  in otm8009a_init_sequence()
190 			 0x00, 0x00, 0x00, 0x00);  in otm8009a_init_sequence()
191 	dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in otm8009a_init_sequence()
192 			 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);  in otm8009a_init_sequence()
193 	dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,  in otm8009a_init_sequence()
194 			 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in otm8009a_init_sequence()
195 	dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,  in otm8009a_init_sequence()
196 			 0x00, 0x00, 0x00, 0x00);  in otm8009a_init_sequence()
197 	dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in otm8009a_init_sequence()
198 			 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);  in otm8009a_init_sequence()
199 	dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,  in otm8009a_init_sequence()
200 			 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in otm8009a_init_sequence()
202 	dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66);  in otm8009a_init_sequence()
204 	dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06);  in otm8009a_init_sequence()
206 	dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,  in otm8009a_init_sequence()
207 			 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,  in otm8009a_init_sequence()
208 			 0x01);  in otm8009a_init_sequence()
209 	dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,  in otm8009a_init_sequence()
210 			 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,  in otm8009a_init_sequence()
211 			 0x01);  in otm8009a_init_sequence()
214 	dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);  in otm8009a_init_sequence()
228 	dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);  in otm8009a_init_sequence()
230 	ret = mipi_dsi_dcs_set_column_address(dsi, 0, OTM8009A_HDISPLAY - 1);  in otm8009a_init_sequence()
234 	ret = mipi_dsi_dcs_set_page_address(dsi, 0, OTM8009A_VDISPLAY - 1);  in otm8009a_init_sequence()
245 	dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);  in otm8009a_init_sequence()
261 	return 0;  in otm8009a_init_sequence()
282 	return 0;  in otm8009a_disable()
298 	return 0;  in otm8009a_unprepare()
307 	if (ret < 0) {  in otm8009a_prepare()
313 		gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in otm8009a_prepare()
316 		gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in otm8009a_prepare()
326 	return 0;  in otm8009a_prepare()
335 	return 0;  in otm8009a_enable()
345 	for (i = 0; i < num_modes; i++) {  in otm8009a_get_modes()
398 		data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;  in otm8009a_backlight_update_status()
403 		data[1] = 0x24;  in otm8009a_backlight_update_status()
407 		data[1] = 0;  in otm8009a_backlight_update_status()
411 	data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;  in otm8009a_backlight_update_status()
414 	return 0;  in otm8009a_backlight_update_status()
475 	if (ret < 0) {  in otm8009a_probe()
481 	return 0;  in otm8009a_probe()