27 #include <nvfw/fw.h>
89 nvkm_gsp_fwsec_patch(struct nvkm_gsp *gsp, struct nvkm_falcon_fw *fw, u32 if_offset, u32 init_cmd)  in nvkm_gsp_fwsec_patch()  argument
91 	union nvfw_falcon_appif_hdr *hdr = (void *)(fw->fw.img + fw->dmem_base_img + if_offset);  in nvkm_gsp_fwsec_patch()
92 	const u8 *dmem = fw->fw.img + fw->dmem_base_img;  in nvkm_gsp_fwsec_patch()
174 		  struct nvkm_falcon_fw *fw)  in nvkm_gsp_fwsec_v2()  argument
185 				  &gsp->falcon, fw);  in nvkm_gsp_fwsec_v2()
189 	fw->nmem_base_img = 0;  in nvkm_gsp_fwsec_v2()
190 	fw->nmem_base = desc->IMEMPhysBase;  in nvkm_gsp_fwsec_v2()
191 	fw->nmem_size = desc->IMEMLoadSize - desc->IMEMSecSize;  in nvkm_gsp_fwsec_v2()
193 	fw->imem_base_img = 0;  in nvkm_gsp_fwsec_v2()
194 	fw->imem_base = desc->IMEMSecBase;  in nvkm_gsp_fwsec_v2()
195 	fw->imem_size = desc->IMEMSecSize;  in nvkm_gsp_fwsec_v2()
197 	fw->dmem_base_img = desc->DMEMOffset;  in nvkm_gsp_fwsec_v2()
198 	fw->dmem_base = desc->DMEMPhysBase;  in nvkm_gsp_fwsec_v2()
199 	fw->dmem_size = desc->DMEMLoadSize;  in nvkm_gsp_fwsec_v2()
209 	fw->boot_addr = bld->start_tag << 8;  in nvkm_gsp_fwsec_v2()
210 	fw->boot_size = bld->code_size;  in nvkm_gsp_fwsec_v2()
211 	fw->boot = kmemdup(bl->data + hdr->data_offset + bld->code_off, fw->boot_size, GFP_KERNEL);  in nvkm_gsp_fwsec_v2()
212 	if (!fw->boot)  in nvkm_gsp_fwsec_v2()
218 	return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd);  in nvkm_gsp_fwsec_v2()
224 		  struct nvkm_falcon_fw *fw)  in nvkm_gsp_fwsec_v3()  argument
233 				  &gsp->falcon, fw);  in nvkm_gsp_fwsec_v3()
237 	fw->imem_base_img = 0;  in nvkm_gsp_fwsec_v3()
238 	fw->imem_base = desc->IMEMPhysBase;  in nvkm_gsp_fwsec_v3()
239 	fw->imem_size = desc->IMEMLoadSize;  in nvkm_gsp_fwsec_v3()
240 	fw->dmem_base_img = desc->IMEMLoadSize;  in nvkm_gsp_fwsec_v3()
241 	fw->dmem_base = desc->DMEMPhysBase;  in nvkm_gsp_fwsec_v3()
242 	fw->dmem_size = ALIGN(desc->DMEMLoadSize, 256);  in nvkm_gsp_fwsec_v3()
243 	fw->dmem_sign = desc->PKCDataOffset;  in nvkm_gsp_fwsec_v3()
244 	fw->boot_addr = 0;  in nvkm_gsp_fwsec_v3()
245 	fw->fuse_ver = desc->SignatureVersions;  in nvkm_gsp_fwsec_v3()
246 	fw->ucode_id = desc->UcodeId;  in nvkm_gsp_fwsec_v3()
247 	fw->engine_id = desc->EngineIdMask;  in nvkm_gsp_fwsec_v3()
250 	ret = nvkm_falcon_fw_sign(fw, fw->dmem_base_img + desc->PKCDataOffset, 96 * 4,  in nvkm_gsp_fwsec_v3()
257 	return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd);  in nvkm_gsp_fwsec_v3()
271 	struct nvkm_falcon_fw fw = {};  in nvkm_gsp_fwsec()  local
293 	case 2: ret = nvkm_gsp_fwsec_v2(gsp, name, &desc->v2, size, init_cmd, &fw); break;  in nvkm_gsp_fwsec()
294 	case 3: ret = nvkm_gsp_fwsec_v3(gsp, name, &desc->v3, size, init_cmd, &fw); break;  in nvkm_gsp_fwsec()
306 	ret = nvkm_falcon_fw_boot(&fw, subdev, true, &mbox0, NULL, 0, 0);  in nvkm_gsp_fwsec()
307 	nvkm_falcon_fw_dtor(&fw);  in nvkm_gsp_fwsec()