43 	ret = nvbios_pll_parse(bios, 0x04, &pll);  in nv40_ram_calc()
50 	if (ret < 0)  in nv40_ram_calc()
53 	ram->ctrl  = 0x80000000 | (log2P << 16);  in nv40_ram_calc()
56 		ram->ctrl |= 0x00000100;  in nv40_ram_calc()
59 		ram->ctrl |= 0x40000000;  in nv40_ram_calc()
63 	return 0;  in nv40_ram_calc()
74 	u32 crtc_mask = 0;  in nv40_ram_prog()
79 	for (i = 0; i < 2; i++) {  in nv40_ram_prog()
80 		u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000));  in nv40_ram_prog()
81 		u32 cnt = 0;  in nv40_ram_prog()
83 			if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) {  in nv40_ram_prog()
84 				nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_ram_prog()
85 				sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000));  in nv40_ram_prog()
86 				if (!(sr1[i] & 0x20))  in nv40_ram_prog()
95 	for (i = 0; i < 2; i++) {  in nv40_ram_prog()
100 			u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));  in nv40_ram_prog()
101 			if (!(tmp & 0x00010000))  in nv40_ram_prog()
106 			u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));  in nv40_ram_prog()
107 			if ( (tmp & 0x00010000))  in nv40_ram_prog()
111 		nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_ram_prog()
112 		nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);  in nv40_ram_prog()
116 	nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */  in nv40_ram_prog()
117 	nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */  in nv40_ram_prog()
118 	nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */  in nv40_ram_prog()
119 	nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */  in nv40_ram_prog()
120 	nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */  in nv40_ram_prog()
123 	nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000);  in nv40_ram_prog()
125 	case 0x40:  in nv40_ram_prog()
126 	case 0x45:  in nv40_ram_prog()
127 	case 0x41:  in nv40_ram_prog()
128 	case 0x42:  in nv40_ram_prog()
129 	case 0x47:  in nv40_ram_prog()
130 		nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
131 		nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
132 		nvkm_wr32(device, 0x004048, ram->coef);  in nv40_ram_prog()
133 		nvkm_wr32(device, 0x004030, ram->coef);  in nv40_ram_prog()
135 	case 0x43:  in nv40_ram_prog()
136 	case 0x49:  in nv40_ram_prog()
137 	case 0x4b:  in nv40_ram_prog()
138 		nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
139 		nvkm_wr32(device, 0x00403c, ram->coef);  in nv40_ram_prog()
142 		nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
143 		nvkm_wr32(device, 0x004024, ram->coef);  in nv40_ram_prog()
147 	nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000);  in nv40_ram_prog()
150 	nvkm_wr32(device, 0x1002dc, 0x00000000);  in nv40_ram_prog()
151 	nvkm_mask(device, 0x100210, 0x80000000, 0x80000000);  in nv40_ram_prog()
156 		nvbios_init(subdev, nvbios_rd16(bios, M.offset + 0x00));  in nv40_ram_prog()
161 	for (i = 0; i < 2; i++) {  in nv40_ram_prog()
166 			u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));  in nv40_ram_prog()
167 			if ( (tmp & 0x00010000))  in nv40_ram_prog()
171 		nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_ram_prog()
172 		nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);  in nv40_ram_prog()
175 	return 0;  in nv40_ram_prog()
205 	u32 pbus1218 = nvkm_rd32(device, 0x001218);  in nv40_ram_new()
206 	u32     size = nvkm_rd32(device, 0x10020c) & 0xff000000;  in nv40_ram_new()
210 	switch (pbus1218 & 0x00000300) {  in nv40_ram_new()
211 	case 0x00000000: type = NVKM_RAM_TYPE_SDRAM; break;  in nv40_ram_new()
212 	case 0x00000100: type = NVKM_RAM_TYPE_DDR1 ; break;  in nv40_ram_new()
213 	case 0x00000200: type = NVKM_RAM_TYPE_GDDR3; break;  in nv40_ram_new()
214 	case 0x00000300: type = NVKM_RAM_TYPE_DDR2 ; break;  in nv40_ram_new()
221 	(*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;  in nv40_ram_new()
222 	return 0;  in nv40_ram_new()