Lines Matching +full:2 +full:khz
100 sdiv = ((sctl & 0x003f0000) >> 16) + 2; in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
171 case 2: in gt215_clk_read()
187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
209 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
210 diff = ((khz + 3000) - oclk); in gt215_clk_info()
216 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
219 /* divider can go as low as 2, limited here because NVIDIA in gt215_clk_info()
224 info->clk = (((sdiv - 2) << 16) | 0x00003100); in gt215_clk_info()
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
246 /* If we can get a within [-2, 3) MHz of a divider, we'll disable the in gt215_pll_info()
248 ret = gt215_clk_info(&clk->base, idx, khz, info); in gt215_pll_info()
249 diff = khz - ret; in gt215_pll_info()
263 ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P); in gt215_pll_info()
269 info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); in gt215_pll_info()
288 u32 kHz = cstate->domain[nv_clk_src_host]; in calc_host() local
291 if (kHz == 277000) { in calc_host()
299 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); in calc_host()