46 	nvkm_wr32(device, device->vfn->addr.user + 0x0090, chan->func->doorbell_handle(chan));  in tu102_chan_start()
67 	return nvkm_rd32(device, 0x002b0c + (runl->id * 0x10)) & 0x00008000;  in tu102_runl_pending()
77 	nvkm_wr32(device, 0x002b00 + (runl->id * 0x10), lower_32_bits(addr));  in tu102_runl_commit()
78 	nvkm_wr32(device, 0x002b04 + (runl->id * 0x10), upper_32_bits(addr));  in tu102_runl_commit()
79 	nvkm_wr32(device, 0x002b08 + (runl->id * 0x10), count);  in tu102_runl_commit()
100 	{ 0x01, "DISPLAY" },
101 	{ 0x03, "PTP" },
102 	{ 0x06, "PWR_PMU" },
103 	{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
104 	{ 0x09, "PERF" },
105 	{ 0x1f, "PHYSICAL" },
106 	{ 0x20, "HOST0" },
107 	{ 0x21, "HOST1" },
108 	{ 0x22, "HOST2" },
109 	{ 0x23, "HOST3" },
110 	{ 0x24, "HOST4" },
111 	{ 0x25, "HOST5" },
112 	{ 0x26, "HOST6" },
113 	{ 0x27, "HOST7" },
114 	{ 0x28, "HOST8" },
115 	{ 0x29, "HOST9" },
116 	{ 0x2a, "HOST10" },
117 	{ 0x2b, "HOST11" },
118 	{ 0x2c, "HOST12" },
119 	{ 0x2d, "HOST13" },
120 	{ 0x2e, "HOST14" },
121 	{ 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
122 	{ 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
145 	if (info & 0xc0000000)  in tu102_fifo_intr_ctxsw_timeout_info()
149 	switch (info & 0x0000c000) {  in tu102_fifo_intr_ctxsw_timeout_info()
150 	case 0x00004000: /* LOAD */  in tu102_fifo_intr_ctxsw_timeout_info()
151 		cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x3fff0000, &flags);  in tu102_fifo_intr_ctxsw_timeout_info()
153 	case 0x00008000: /* SAVE */  in tu102_fifo_intr_ctxsw_timeout_info()
154 	case 0x0000c000: /* SWITCH */  in tu102_fifo_intr_ctxsw_timeout_info()
155 		cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x00003fff, &flags);  in tu102_fifo_intr_ctxsw_timeout_info()
174 	u32 engm = nvkm_rd32(device, 0x002a30);  in tu102_fifo_intr_ctxsw_timeout()
179 			info = nvkm_rd32(device, 0x003200 + (engn->id * 4));  in tu102_fifo_intr_ctxsw_timeout()
184 	nvkm_wr32(device, 0x002a30, engm);  in tu102_fifo_intr_ctxsw_timeout()
191 	u32 intr = nvkm_rd32(subdev->device, 0x00254c);  in tu102_fifo_intr_sched()
192 	u32 code = intr & 0x000000ff;  in tu102_fifo_intr_sched()
203 	u32 mask = nvkm_rd32(device, 0x002140);  in tu102_fifo_intr()
204 	u32 stat = nvkm_rd32(device, 0x002100) & mask;  in tu102_fifo_intr()
206 	if (stat & 0x00000001) {  in tu102_fifo_intr()
208 		nvkm_wr32(device, 0x002100, 0x00000001);  in tu102_fifo_intr()
209 		stat &= ~0x00000001;  in tu102_fifo_intr()
212 	if (stat & 0x00000002) {  in tu102_fifo_intr()
214 		stat &= ~0x00000002;  in tu102_fifo_intr()
217 	if (stat & 0x00000100) {  in tu102_fifo_intr()
219 		nvkm_wr32(device, 0x002100, 0x00000100);  in tu102_fifo_intr()
220 		stat &= ~0x00000100;  in tu102_fifo_intr()
223 	if (stat & 0x00010000) {  in tu102_fifo_intr()
225 		nvkm_wr32(device, 0x002100, 0x00010000);  in tu102_fifo_intr()
226 		stat &= ~0x00010000;  in tu102_fifo_intr()
229 	if (stat & 0x20000000) {  in tu102_fifo_intr()
231 			stat &= ~0x20000000;  in tu102_fifo_intr()
234 	if (stat & 0x40000000) {  in tu102_fifo_intr()
236 		stat &= ~0x40000000;  in tu102_fifo_intr()
239 	if (stat & 0x80000000) {  in tu102_fifo_intr()
240 		nvkm_wr32(device, 0x002100, 0x80000000);  in tu102_fifo_intr()
241 		nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT);  in tu102_fifo_intr()
242 		stat &= ~0x80000000;  in tu102_fifo_intr()
248 		nvkm_mask(device, 0x002140, stat, 0x00000000);  in tu102_fifo_intr()
250 		nvkm_wr32(device, 0x002100, stat);  in tu102_fifo_intr()
260 	nvkm_mask(fifo->engine.subdev.device, 0xb65000, 0x80000000, 0x80000000);  in tu102_fifo_init_pbdmas()
278 	.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp, .force = true },
279 	.chan = {{ 0, 0, TURING_CHANNEL_GPFIFO_A }, &tu102_chan },