47 	nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd));  in gv100_chan_ramfc_write()
48 	nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd));  in gv100_chan_ramfc_write()
49 	nvkm_wo32(chan->inst, 0x010, 0x0000face);  in gv100_chan_ramfc_write()
50 	nvkm_wo32(chan->inst, 0x030, 0x7ffff902);  in gv100_chan_ramfc_write()
51 	nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));  in gv100_chan_ramfc_write()
52 	nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));  in gv100_chan_ramfc_write()
53 	nvkm_wo32(chan->inst, 0x084, 0x20400000);  in gv100_chan_ramfc_write()
54 	nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);  in gv100_chan_ramfc_write()
55 	nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);  in gv100_chan_ramfc_write()
56 	nvkm_wo32(chan->inst, 0x0e8, chan->id);  in gv100_chan_ramfc_write()
57 	nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));  in gv100_chan_ramfc_write()
58 	nvkm_wo32(chan->inst, 0x0f8, 0x10003080);  in gv100_chan_ramfc_write()
59 	nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);  in gv100_chan_ramfc_write()
61 	return 0;  in gv100_chan_ramfc_write()
67 	.devm = 0xfff,
74 	.size = 0x200,
94 	u64 addr = 0ULL;  in gv100_ectx_bind()
102 	nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr));  in gv100_ectx_bind()
103 	nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr));  in gv100_ectx_bind()
104 	nvkm_mo32(chan->inst, 0x0ac, 0x00010000, cctx ? 0x00010000 : 0x00000000);  in gv100_ectx_bind()
119 	const u64 bar2 = cctx ? nvkm_memory_bar2(cctx->vctx->inst->memory) : 0ULL;  in gv100_ectx_ce_bind()
122 	nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2));  in gv100_ectx_ce_bind()
123 	nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2));  in gv100_ectx_ce_bind()
124 	nvkm_mo32(chan->inst, 0x0ac, 0x00020000, cctx ? 0x00020000 : 0x00000000);  in gv100_ectx_ce_bind()
131 	if (nvkm_memory_bar2(vctx->inst->memory) == ~0ULL)  in gv100_ectx_ce_ctor()
134 	return 0;  in gv100_ectx_ce_ctor()
162 	nvkm_mask(device, 0x0400ac + (runq->id * 0x2000), 0x00030000, 0x00030000);  in gv100_runq_intr_1_ctxnotvalid()
163 	nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0x80000000);  in gv100_runq_intr_1_ctxnotvalid()
179 	nvkm_wr32(runl->fifo->engine.subdev.device, 0x002638, BIT(runl->id));  in gv100_runl_preempt()
188 	nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1);  in gv100_runl_insert_chan()
189 	nvkm_wo32(memory, offset + 0x4, upper_32_bits(user));  in gv100_runl_insert_chan()
190 	nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id);  in gv100_runl_insert_chan()
191 	nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));  in gv100_runl_insert_chan()
197 	nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001);  in gv100_runl_insert_cgrp()
198 	nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr);  in gv100_runl_insert_cgrp()
199 	nvkm_wo32(memory, offset + 0x8, cgrp->id);  in gv100_runl_insert_cgrp()
200 	nvkm_wo32(memory, offset + 0xc, 0x00000000);  in gv100_runl_insert_cgrp()
221 	{ 0x00, "T1_0" },
222 	{ 0x01, "T1_1" },
223 	{ 0x02, "T1_2" },
224 	{ 0x03, "T1_3" },
225 	{ 0x04, "T1_4" },
226 	{ 0x05, "T1_5" },
227 	{ 0x06, "T1_6" },
228 	{ 0x07, "T1_7" },
229 	{ 0x08, "PE_0" },
230 	{ 0x09, "PE_1" },
231 	{ 0x0a, "PE_2" },
232 	{ 0x0b, "PE_3" },
233 	{ 0x0c, "PE_4" },
234 	{ 0x0d, "PE_5" },
235 	{ 0x0e, "PE_6" },
236 	{ 0x0f, "PE_7" },
237 	{ 0x10, "RAST" },
238 	{ 0x11, "GCC" },
239 	{ 0x12, "GPCCS" },
240 	{ 0x13, "PROP_0" },
241 	{ 0x14, "PROP_1" },
242 	{ 0x15, "PROP_2" },
243 	{ 0x16, "PROP_3" },
244 	{ 0x17, "GPM" },
245 	{ 0x18, "LTP_UTLB_0" },
246 	{ 0x19, "LTP_UTLB_1" },
247 	{ 0x1a, "LTP_UTLB_2" },
248 	{ 0x1b, "LTP_UTLB_3" },
249 	{ 0x1c, "LTP_UTLB_4" },
250 	{ 0x1d, "LTP_UTLB_5" },
251 	{ 0x1e, "LTP_UTLB_6" },
252 	{ 0x1f, "LTP_UTLB_7" },
253 	{ 0x20, "RGG_UTLB" },
254 	{ 0x21, "T1_8" },
255 	{ 0x22, "T1_9" },
256 	{ 0x23, "T1_10" },
257 	{ 0x24, "T1_11" },
258 	{ 0x25, "T1_12" },
259 	{ 0x26, "T1_13" },
260 	{ 0x27, "T1_14" },
261 	{ 0x28, "T1_15" },
262 	{ 0x29, "TPCCS_0" },
263 	{ 0x2a, "TPCCS_1" },
264 	{ 0x2b, "TPCCS_2" },
265 	{ 0x2c, "TPCCS_3" },
266 	{ 0x2d, "TPCCS_4" },
267 	{ 0x2e, "TPCCS_5" },
268 	{ 0x2f, "TPCCS_6" },
269 	{ 0x30, "TPCCS_7" },
270 	{ 0x31, "PE_8" },
271 	{ 0x32, "PE_9" },
272 	{ 0x33, "TPCCS_8" },
273 	{ 0x34, "TPCCS_9" },
274 	{ 0x35, "T1_16" },
275 	{ 0x36, "T1_17" },
276 	{ 0x37, "T1_18" },
277 	{ 0x38, "T1_19" },
278 	{ 0x39, "PE_10" },
279 	{ 0x3a, "PE_11" },
280 	{ 0x3b, "TPCCS_10" },
281 	{ 0x3c, "TPCCS_11" },
282 	{ 0x3d, "T1_20" },
283 	{ 0x3e, "T1_21" },
284 	{ 0x3f, "T1_22" },
285 	{ 0x40, "T1_23" },
286 	{ 0x41, "PE_12" },
287 	{ 0x42, "PE_13" },
288 	{ 0x43, "TPCCS_12" },
289 	{ 0x44, "TPCCS_13" },
290 	{ 0x45, "T1_24" },
291 	{ 0x46, "T1_25" },
292 	{ 0x47, "T1_26" },
293 	{ 0x48, "T1_27" },
294 	{ 0x49, "PE_14" },
295 	{ 0x4a, "PE_15" },
296 	{ 0x4b, "TPCCS_14" },
297 	{ 0x4c, "TPCCS_15" },
298 	{ 0x4d, "T1_28" },
299 	{ 0x4e, "T1_29" },
300 	{ 0x4f, "T1_30" },
301 	{ 0x50, "T1_31" },
302 	{ 0x51, "PE_16" },
303 	{ 0x52, "PE_17" },
304 	{ 0x53, "TPCCS_16" },
305 	{ 0x54, "TPCCS_17" },
306 	{ 0x55, "T1_32" },
307 	{ 0x56, "T1_33" },
308 	{ 0x57, "T1_34" },
309 	{ 0x58, "T1_35" },
310 	{ 0x59, "PE_18" },
311 	{ 0x5a, "PE_19" },
312 	{ 0x5b, "TPCCS_18" },
313 	{ 0x5c, "TPCCS_19" },
314 	{ 0x5d, "T1_36" },
315 	{ 0x5e, "T1_37" },
316 	{ 0x5f, "T1_38" },
317 	{ 0x60, "T1_39" },
323 	{ 0x00, "VIP" },
324 	{ 0x01, "CE0" },
325 	{ 0x02, "CE1" },
326 	{ 0x03, "DNISO" },
327 	{ 0x04, "FE" },
328 	{ 0x05, "FECS" },
329 	{ 0x06, "HOST" },
330 	{ 0x07, "HOST_CPU" },
331 	{ 0x08, "HOST_CPU_NB" },
332 	{ 0x09, "ISO" },
333 	{ 0x0a, "MMU" },
334 	{ 0x0b, "NVDEC" },
335 	{ 0x0d, "NVENC1" },
336 	{ 0x0e, "NISO" },
337 	{ 0x0f, "P2P" },
338 	{ 0x10, "PD" },
339 	{ 0x11, "PERF" },
340 	{ 0x12, "PMU" },
341 	{ 0x13, "RASTERTWOD" },
342 	{ 0x14, "SCC" },
343 	{ 0x15, "SCC_NB" },
344 	{ 0x16, "SEC" },
345 	{ 0x17, "SSYNC" },
346 	{ 0x18, "CE2" },
347 	{ 0x19, "XV" },
348 	{ 0x1a, "MMU_NB" },
349 	{ 0x1b, "NVENC0" },
350 	{ 0x1c, "DFALCON" },
351 	{ 0x1d, "SKED" },
352 	{ 0x1e, "AFALCON" },
353 	{ 0x1f, "DONT_CARE" },
354 	{ 0x20, "HSCE0" },
355 	{ 0x21, "HSCE1" },
356 	{ 0x22, "HSCE2" },
357 	{ 0x23, "HSCE3" },
358 	{ 0x24, "HSCE4" },
359 	{ 0x25, "HSCE5" },
360 	{ 0x26, "HSCE6" },
361 	{ 0x27, "HSCE7" },
362 	{ 0x28, "HSCE8" },
363 	{ 0x29, "HSCE9" },
364 	{ 0x2a, "HSHUB" },
365 	{ 0x2b, "PTP_X0" },
366 	{ 0x2c, "PTP_X1" },
367 	{ 0x2d, "PTP_X2" },
368 	{ 0x2e, "PTP_X3" },
369 	{ 0x2f, "PTP_X4" },
370 	{ 0x30, "PTP_X5" },
371 	{ 0x31, "PTP_X6" },
372 	{ 0x32, "PTP_X7" },
373 	{ 0x33, "NVENC2" },
374 	{ 0x34, "VPR_SCRUBBER0" },
375 	{ 0x35, "VPR_SCRUBBER1" },
376 	{ 0x36, "DWBIF" },
377 	{ 0x37, "FBFALCON" },
378 	{ 0x38, "CE_SHIM" },
379 	{ 0x39, "GSP" },
385 	{ 0x00, "PDE" },
386 	{ 0x01, "PDE_SIZE" },
387 	{ 0x02, "PTE" },
388 	{ 0x03, "VA_LIMIT_VIOLATION" },
389 	{ 0x04, "UNBOUND_INST_BLOCK" },
390 	{ 0x05, "PRIV_VIOLATION" },
391 	{ 0x06, "RO_VIOLATION" },
392 	{ 0x07, "WO_VIOLATION" },
393 	{ 0x08, "PITCH_MASK_VIOLATION" },
394 	{ 0x09, "WORK_CREATION" },
395 	{ 0x0a, "UNSUPPORTED_APERTURE" },
396 	{ 0x0b, "COMPRESSION_FAILURE" },
397 	{ 0x0c, "UNSUPPORTED_KIND" },
398 	{ 0x0d, "REGION_VIOLATION" },
399 	{ 0x0e, "POISONED" },
400 	{ 0x0f, "ATOMIC_VIOLATION" },
406 	{ 0x01, "DISPLAY" },
407 	{ 0x03, "PTP" },
408 	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
409 	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
410 	{ 0x06, "PWR_PMU" },
411 	{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
412 	{ 0x09, "PERF" },
413 	{ 0x1f, "PHYSICAL" },
414 	{ 0x20, "HOST0" },
415 	{ 0x21, "HOST1" },
416 	{ 0x22, "HOST2" },
417 	{ 0x23, "HOST3" },
418 	{ 0x24, "HOST4" },
419 	{ 0x25, "HOST5" },
420 	{ 0x26, "HOST6" },
421 	{ 0x27, "HOST7" },
422 	{ 0x28, "HOST8" },
423 	{ 0x29, "HOST9" },
424 	{ 0x2a, "HOST10" },
425 	{ 0x2b, "HOST11" },
426 	{ 0x2c, "HOST12" },
427 	{ 0x2d, "HOST13" },
433 	{ 0x0, "VIRT_READ" },
434 	{ 0x1, "VIRT_WRITE" },
435 	{ 0x2, "VIRT_ATOMIC" },
436 	{ 0x3, "VIRT_PREFETCH" },
437 	{ 0x4, "VIRT_ATOMIC_WEAK" },
438 	{ 0x8, "PHYS_READ" },
439 	{ 0x9, "PHYS_WRITE" },
440 	{ 0xa, "PHYS_ATOMIC" },
441 	{ 0xb, "PHYS_PREFETCH" },
483 	.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp, .force = true },
484 	.chan = {{ 0, 0,  VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan },