Lines Matching +full:0 +full:xfffff000
46 u64 offset = dmaobj->base.start & 0xfffff000; in nv04_dmaobj_bind()
47 u64 adjust = dmaobj->base.start & 0x00000fff; in nv04_dmaobj_bind()
53 device->mmu->vmm->pd->pt[0]->memory; in nv04_dmaobj_bind()
58 offset &= 0xfffff000; in nv04_dmaobj_bind()
63 if (ret == 0) { in nv04_dmaobj_bind()
65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
66 nvkm_wo32(*pgpuobj, 0x04, length); in nv04_dmaobj_bind()
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
107 dmaobj->flags0 |= 0x00003000; in nv04_dmaobj_new()
110 dmaobj->flags0 |= 0x00023000; in nv04_dmaobj_new()
113 dmaobj->flags0 |= 0x00033000; in nv04_dmaobj_new()
121 dmaobj->flags0 |= 0x00004000; in nv04_dmaobj_new()
124 dmaobj->flags0 |= 0x00008000; in nv04_dmaobj_new()
127 dmaobj->flags2 |= 0x00000002; in nv04_dmaobj_new()
133 return 0; in nv04_dmaobj_new()