77 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
98 static int nouveau_noaccel = 0;
102 		          "0 = disabled, 1 = enabled, 2 = headless)");
107 static int nouveau_atomic = 0;
110 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
287 	if (ret < 0) {  in nouveau_cli_init()
299 	if (ret < 0) {  in nouveau_cli_init()
320 	return 0;  in nouveau_cli_init()
340 	int ret = 0;  in nouveau_accel_ce_init()
393 				       NULL, 0, &drm->channel->nvsw);  in nouveau_accel_gr_init()
395 		if (ret == 0 && device->info.chipset >= 0x11) {  in nouveau_accel_gr_init()
397 					       0x005f, 0x009f,  in nouveau_accel_gr_init()
398 					       NULL, 0, &drm->channel->blit);  in nouveau_accel_gr_init()
401 		if (ret == 0) {  in nouveau_accel_gr_init()
405 			if (ret == 0) {  in nouveau_accel_gr_init()
406 				if (device->info.chipset >= 0x11) {  in nouveau_accel_gr_init()
407 					PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);  in nouveau_accel_gr_init()
408 					PUSH_NVSQ(push, NV09F, 0x0120, 0,  in nouveau_accel_gr_init()
409 							       0x0124, 1,  in nouveau_accel_gr_init()
410 							       0x0128, 2);  in nouveau_accel_gr_init()
412 				PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);  in nouveau_accel_gr_init()
428 		ret = nvkm_gpuobj_new(nvxx_device(drm), 32, 0, false, NULL, &drm->notify);  in nouveau_accel_gr_init()
480 	if (ret < 0)  in nouveau_accel_init()
483 	for (ret = -ENOSYS, i = 0; i < n; i++) {  in nouveau_accel_init()
629 	drm->sched_wq = alloc_workqueue("nouveau_sched_wq_shared", 0,  in nouveau_drm_device_init()
646 	if (drm->client.device.info.chipset == 0xc1)  in nouveau_drm_device_init()
647 		nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);  in nouveau_drm_device_init()
686 	ret = drm_dev_register(drm->dev, 0);  in nouveau_drm_device_init()
692 	return 0;  in nouveau_drm_device_init()
774 	if (ret < 0) {  in nouveau_drm_device_new()
811  * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
812  * documented PCI config space register 0x248 of the Intel PCIe bridge
813  * controller (0x1901) in order to change the state of the PCIe link between
816  *  - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
817  *  - 0xb0 bit 0x10 (link disable)
822  * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
843 	case 0x1901:  in quirk_broken_nv_runpm()
845 		pdev->pm_cap = 0;  in quirk_broken_nv_runpm()
901 	return 0;  in nouveau_drm_probe()
985 	return 0;  in nouveau_do_suspend()
1003 	int ret = 0;  in nouveau_do_resume()
1026 	return 0;  in nouveau_do_resume()
1038 		return 0;  in nouveau_pmops_suspend()
1048 	return 0;  in nouveau_pmops_suspend()
1060 		return 0;  in nouveau_pmops_resume()
1150 	nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));  in nouveau_pmops_runtime_resume()
1183 	if (ret < 0 && ret != -EACCES) {  in nouveau_drm_open()
1282 	if (ret < 0 && ret != -EACCES) {  in nouveau_drm_ioctl()
1354 		.class_mask  = 0xff << 16,
1359 		.class_mask  = 0xff << 16,
1445 			nouveau_modeset = 0;  in nouveau_drm_init()
1449 		return 0;  in nouveau_drm_init()
1470 	return 0;  in nouveau_drm_init()