Lines Matching +full:dp +full:- +full:aux +full:- +full:bus
32 #include <linux/dma-mapping.h>
84 chan->device = device; in nv50_chan_create()
95 &chan->user); in nv50_chan_create()
97 ret = nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
99 nvif_object_dtor(&chan->user); in nv50_chan_create()
109 return -ENOSYS; in nv50_chan_create()
115 nvif_object_dtor(&chan->user); in nv50_chan_destroy()
125 nvif_object_dtor(&dmac->vram); in nv50_dmac_destroy()
126 nvif_object_dtor(&dmac->sync); in nv50_dmac_destroy()
128 nv50_chan_destroy(&dmac->base); in nv50_dmac_destroy()
130 nvif_mem_dtor(&dmac->push.mem); in nv50_dmac_destroy()
138 dmac->cur = push->cur - (u32 __iomem *)dmac->push.mem.object.map.ptr; in nv50_dmac_kick()
139 if (dmac->put != dmac->cur) { in nv50_dmac_kick()
143 if (dmac->push.mem.type & NVIF_MEM_VRAM) { in nv50_dmac_kick()
144 struct nvif_device *device = dmac->base.device; in nv50_dmac_kick()
145 nvif_wr32(&device->object, 0x070000, 0x00000001); in nv50_dmac_kick()
147 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()
152 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); in nv50_dmac_kick()
153 dmac->put = dmac->cur; in nv50_dmac_kick()
156 push->bgn = push->cur; in nv50_dmac_kick()
162 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); in nv50_dmac_free()
163 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ in nv50_dmac_free()
164 return get - dmac->cur - 5; in nv50_dmac_free()
165 return dmac->max - dmac->cur; in nv50_dmac_free()
174 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); in nv50_dmac_wind()
176 /* Corner-case, HW idle, but non-committed work pending. */ in nv50_dmac_wind()
177 if (dmac->put == 0) in nv50_dmac_wind()
178 nv50_dmac_kick(&dmac->push); in nv50_dmac_wind()
180 if (nvif_msec(dmac->base.device, 2000, in nv50_dmac_wind()
181 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) in nv50_dmac_wind()
184 return -ETIMEDOUT; in nv50_dmac_wind()
187 PUSH_RSVD(&dmac->push, PUSH_JUMP(&dmac->push, 0)); in nv50_dmac_wind()
188 dmac->cur = 0; in nv50_dmac_wind()
198 if (WARN_ON(size > dmac->max)) in nv50_dmac_wait()
199 return -EINVAL; in nv50_dmac_wait()
201 dmac->cur = push->cur - (u32 __iomem *)dmac->push.mem.object.map.ptr; in nv50_dmac_wait()
202 if (dmac->cur + size >= dmac->max) { in nv50_dmac_wait()
207 push->cur = dmac->push.mem.object.map.ptr; in nv50_dmac_wait()
208 push->cur = push->cur + dmac->cur; in nv50_dmac_wait()
212 if (nvif_msec(dmac->base.device, 2000, in nv50_dmac_wait()
217 return -ETIMEDOUT; in nv50_dmac_wait()
220 push->bgn = dmac->push.mem.object.map.ptr; in nv50_dmac_wait()
221 push->bgn = push->bgn + dmac->cur; in nv50_dmac_wait()
222 push->cur = push->bgn; in nv50_dmac_wait()
223 push->end = push->cur + free; in nv50_dmac_wait()
228 static int nv50_dmac_vram_pushbuf = -1;
236 struct nvif_device *device = &drm->device; in nv50_dmac_create()
237 struct nvif_object *disp = &drm->display->disp.object; in nv50_dmac_create()
242 /* Pascal added support for 47-bit physical addresses, but some in nv50_dmac_create()
243 * parts of EVO still only accept 40-bit PAs. in nv50_dmac_create()
252 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) in nv50_dmac_create()
255 ret = nvif_mem_ctor_map(&drm->mmu, "kmsChanPush", type, 0x1000, &dmac->push.mem); in nv50_dmac_create()
259 dmac->push.wait = nv50_dmac_wait; in nv50_dmac_create()
260 dmac->push.kick = nv50_dmac_kick; in nv50_dmac_create()
261 dmac->push.bgn = dmac->push.mem.object.map.ptr; in nv50_dmac_create()
262 dmac->push.cur = dmac->push.bgn; in nv50_dmac_create()
263 dmac->push.end = dmac->push.bgn; in nv50_dmac_create()
264 dmac->max = 0x1000/4 - 1; in nv50_dmac_create()
269 if (disp->oclass < GV100_DISP) in nv50_dmac_create()
270 dmac->max -= 12; in nv50_dmac_create()
272 args->pushbuf = nvif_handle(&dmac->push.mem.object); in nv50_dmac_create()
275 &dmac->base); in nv50_dmac_create()
282 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, in nv50_dmac_create()
290 &dmac->sync); in nv50_dmac_create()
294 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, in nv50_dmac_create()
300 .limit = device->info.ram_user - 1, in nv50_dmac_create()
302 &dmac->vram); in nv50_dmac_create()
317 outp->base.base.name, outp->caps.dp_interlace); in nv50_outp_dump_caps()
326 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; in nv50_outp_atomic_check_view()
327 struct drm_display_mode *mode = &crtc_state->mode; in nv50_outp_atomic_check_view()
328 struct drm_connector *connector = conn_state->connector; in nv50_outp_atomic_check_view()
330 struct nouveau_drm *drm = nouveau_drm(encoder->dev); in nv50_outp_atomic_check_view()
332 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); in nv50_outp_atomic_check_view()
333 asyc->scaler.full = false; in nv50_outp_atomic_check_view()
337 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { in nv50_outp_atomic_check_view()
338 switch (connector->connector_type) { in nv50_outp_atomic_check_view()
345 if (mode->hdisplay == native_mode->hdisplay && in nv50_outp_atomic_check_view()
346 mode->vdisplay == native_mode->vdisplay && in nv50_outp_atomic_check_view()
347 mode->type & DRM_MODE_TYPE_DRIVER) in nv50_outp_atomic_check_view()
350 asyc->scaler.full = true; in nv50_outp_atomic_check_view()
361 crtc_state->mode_changed = true; in nv50_outp_atomic_check_view()
372 struct drm_display_mode *mode = &asyh->state.adjusted_mode; in nv50_outp_atomic_fix_depth()
375 switch (nv_encoder->dcb->type) { in nv50_outp_atomic_fix_depth()
377 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw; in nv50_outp_atomic_fix_depth()
380 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10); in nv50_outp_atomic_fix_depth()
383 while (asyh->or.bpc > 6) { in nv50_outp_atomic_fix_depth()
384 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8); in nv50_outp_atomic_fix_depth()
388 asyh->or.bpc -= 2; in nv50_outp_atomic_fix_depth()
401 struct drm_connector *connector = conn_state->connector; in nv50_outp_atomic_check()
407 nv_connector->native_mode); in nv50_outp_atomic_check()
411 if (crtc_state->mode_changed || crtc_state->connectors_changed) in nv50_outp_atomic_check()
412 asyh->or.bpc = connector->display_info.bpc; in nv50_outp_atomic_check()
429 if (connector_state->best_encoder == encoder) in nv50_outp_get_new_connector()
445 if (connector_state->best_encoder == encoder) in nv50_outp_get_old_connector()
457 const u32 mask = drm_encoder_mask(&outp->base.base); in nv50_outp_get_new_crtc()
461 if (crtc_state->encoder_mask & mask) in nv50_outp_get_new_crtc()
475 struct nv50_core *core = nv50_disp(encoder->dev)->core; in nv50_dac_atomic_disable()
478 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL); in nv50_dac_atomic_disable()
479 nv_encoder->crtc = NULL; in nv50_dac_atomic_disable()
488 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); in nv50_dac_atomic_enable()
489 struct nv50_core *core = nv50_disp(encoder->dev)->core; in nv50_dac_atomic_enable()
492 switch (nv_crtc->index) { in nv50_dac_atomic_enable()
504 if (!nvif_outp_acquired(&nv_encoder->outp)) in nv50_dac_atomic_enable()
505 nvif_outp_acquire_dac(&nv_encoder->outp); in nv50_dac_atomic_enable()
507 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); in nv50_dac_atomic_enable()
508 asyh->or.depth = 0; in nv50_dac_atomic_enable()
510 nv_encoder->crtc = &nv_crtc->base; in nv50_dac_atomic_enable()
520 loadval = nouveau_drm(encoder->dev)->vbios.dactestval; in nv50_dac_detect()
524 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval); in nv50_dac_detect()
544 nvif_outp_dtor(&nv_encoder->outp); in nv50_dac_destroy()
558 struct drm_connector *connector = &nv_encoder->conn->base; in nv50_dac_create()
559 struct nouveau_drm *drm = nouveau_drm(connector->dev); in nv50_dac_create()
561 struct nvkm_i2c_bus *bus; in nv50_dac_create() local
563 struct dcb_output *dcbe = nv_encoder->dcb; in nv50_dac_create()
566 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); in nv50_dac_create()
567 if (bus) in nv50_dac_create()
568 nv_encoder->i2c = &bus->i2c; in nv50_dac_create()
571 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, in nv50_dac_create()
572 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); in nv50_dac_create()
586 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) in nv50_audio_component_eld_notify()
587 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, in nv50_audio_component_eld_notify()
603 mutex_lock(&drm->audio.lock); in nv50_audio_component_get_eld()
605 drm_for_each_encoder(encoder, drm->dev) { in nv50_audio_component_get_eld()
608 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) in nv50_audio_component_get_eld()
612 nv_connector = nv_encoder->conn; in nv50_audio_component_get_eld()
613 nv_crtc = nouveau_crtc(nv_encoder->crtc); in nv50_audio_component_get_eld()
615 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id) in nv50_audio_component_get_eld()
618 *enabled = nv_encoder->audio.enabled; in nv50_audio_component_get_eld()
620 ret = drm_eld_size(nv_connector->base.eld); in nv50_audio_component_get_eld()
621 memcpy(buf, nv_connector->base.eld, in nv50_audio_component_get_eld()
627 mutex_unlock(&drm->audio.lock); in nv50_audio_component_get_eld()
644 return -ENOMEM; in nv50_audio_component_bind()
646 drm_modeset_lock_all(drm->dev); in nv50_audio_component_bind()
647 acomp->ops = &nv50_audio_component_ops; in nv50_audio_component_bind()
648 acomp->dev = kdev; in nv50_audio_component_bind()
649 drm->audio.component = acomp; in nv50_audio_component_bind()
650 drm_modeset_unlock_all(drm->dev); in nv50_audio_component_bind()
661 drm_modeset_lock_all(drm->dev); in nv50_audio_component_unbind()
662 drm->audio.component = NULL; in nv50_audio_component_unbind()
663 acomp->ops = NULL; in nv50_audio_component_unbind()
664 acomp->dev = NULL; in nv50_audio_component_unbind()
665 drm_modeset_unlock_all(drm->dev); in nv50_audio_component_unbind()
676 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) in nv50_audio_component_init()
679 drm->audio.component_registered = true; in nv50_audio_component_init()
680 mutex_init(&drm->audio.lock); in nv50_audio_component_init()
686 if (!drm->audio.component_registered) in nv50_audio_component_fini()
689 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); in nv50_audio_component_fini()
690 drm->audio.component_registered = false; in nv50_audio_component_fini()
691 mutex_destroy(&drm->audio.lock); in nv50_audio_component_fini()
700 struct nv50_disp *disp = nv50_disp(encoder->dev); in nv50_audio_supported()
702 if (disp->disp->object.oclass <= GT200_DISP || in nv50_audio_supported()
703 disp->disp->object.oclass == GT206_DISP) in nv50_audio_supported()
706 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { in nv50_audio_supported()
709 switch (nv_encoder->dcb->type) { in nv50_audio_supported()
724 struct nouveau_drm *drm = nouveau_drm(encoder->dev); in nv50_audio_disable()
726 struct nvif_outp *outp = &nv_encoder->outp; in nv50_audio_disable()
731 mutex_lock(&drm->audio.lock); in nv50_audio_disable()
732 if (nv_encoder->audio.enabled) { in nv50_audio_disable()
733 nv_encoder->audio.enabled = false; in nv50_audio_disable()
734 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0); in nv50_audio_disable()
736 mutex_unlock(&drm->audio.lock); in nv50_audio_disable()
738 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index); in nv50_audio_disable()
746 struct nouveau_drm *drm = nouveau_drm(encoder->dev); in nv50_audio_enable()
748 struct nvif_outp *outp = &nv_encoder->outp; in nv50_audio_enable()
750 if (!nv50_audio_supported(encoder) || !nv_connector->base.display_info.has_audio) in nv50_audio_enable()
753 mutex_lock(&drm->audio.lock); in nv50_audio_enable()
755 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld, in nv50_audio_enable()
756 drm_eld_size(nv_connector->base.eld)); in nv50_audio_enable()
757 nv_encoder->audio.enabled = true; in nv50_audio_enable()
759 mutex_unlock(&drm->audio.lock); in nv50_audio_enable()
761 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index); in nv50_audio_enable()
772 struct nouveau_drm *drm = nouveau_drm(encoder->dev); in nv50_hdmi_enable()
774 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi; in nv50_hdmi_enable()
784 max_ac_packet = mode->htotal - mode->hdisplay; in nv50_hdmi_enable()
785 max_ac_packet -= rekey; in nv50_hdmi_enable()
786 max_ac_packet -= 18; /* constant from tegra */ in nv50_hdmi_enable()
789 if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) { in nv50_hdmi_enable()
790 const bool high_tmds_clock_ratio = mode->clock > 340000; in nv50_hdmi_enable()
793 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc); in nv50_hdmi_enable()
800 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates) in nv50_hdmi_enable()
805 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc); in nv50_hdmi_enable()
811 ret = nvif_outp_hdmi(&nv_encoder->outp, nv_crtc->index, true, max_ac_packet, rekey, in nv50_hdmi_enable()
812 mode->clock, hdmi->scdc.supported, hdmi->scdc.scrambling.supported, in nv50_hdmi_enable()
813 hdmi->scdc.scrambling.low_rates); in nv50_hdmi_enable()
819 args.infoframe.head = nv_crtc->index; in nv50_hdmi_enable()
821 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) { in nv50_hdmi_enable()
822 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode, in nv50_hdmi_enable()
830 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size); in nv50_hdmi_enable()
835 &nv_connector->base, mode)) in nv50_hdmi_enable()
840 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size); in nv50_hdmi_enable()
842 nv_encoder->hdmi.enabled = true; in nv50_hdmi_enable()
877 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) in nv50_real_outp()
881 if (!msto->mstc) in nv50_real_outp()
883 return msto->mstc->mstm->outp; in nv50_real_outp()
892 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); in nv50_msto_cleanup()
894 drm_atomic_get_mst_payload_state(new_mst_state, msto->mstc->port); in nv50_msto_cleanup()
898 drm_atomic_get_mst_payload_state(old_mst_state, msto->mstc->port); in nv50_msto_cleanup()
899 struct nv50_mstc *mstc = msto->mstc; in nv50_msto_cleanup()
900 struct nv50_mstm *mstm = mstc->mstm; in nv50_msto_cleanup()
902 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); in nv50_msto_cleanup()
904 if (msto->disabled) { in nv50_msto_cleanup()
905 if (msto->head->func->display_id) { in nv50_msto_cleanup()
906 nvif_outp_dp_mst_id_put(&mstm->outp->outp, msto->display_id); in nv50_msto_cleanup()
907 msto->display_id = 0; in nv50_msto_cleanup()
910 msto->mstc = NULL; in nv50_msto_cleanup()
911 msto->disabled = false; in nv50_msto_cleanup()
913 } else if (msto->enabled) { in nv50_msto_cleanup()
915 msto->enabled = false; in nv50_msto_cleanup()
925 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); in nv50_msto_prepare()
926 struct nv50_mstc *mstc = msto->mstc; in nv50_msto_prepare()
927 struct nv50_mstm *mstm = mstc->mstm; in nv50_msto_prepare()
931 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); in nv50_msto_prepare()
933 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port); in nv50_msto_prepare()
935 if (msto->disabled) { in nv50_msto_prepare()
937 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); in nv50_msto_prepare()
940 if (msto->enabled) in nv50_msto_prepare()
945 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, in nv50_msto_prepare()
946 payload->vc_start_slot, payload->time_slots, in nv50_msto_prepare()
947 payload->pbn, in nv50_msto_prepare()
948 payload->time_slots * dfixed_trunc(mst_state->pbn_div)); in nv50_msto_prepare()
950 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); in nv50_msto_prepare()
959 struct drm_atomic_state *state = crtc_state->state; in nv50_msto_atomic_check()
960 struct drm_connector *connector = conn_state->connector; in nv50_msto_atomic_check()
963 struct nv50_mstm *mstm = mstc->mstm; in nv50_msto_atomic_check()
969 mstc->native); in nv50_msto_atomic_check()
981 if (!state->duplicated) { in nv50_msto_atomic_check()
982 const int clock = crtc_state->adjusted_mode.clock; in nv50_msto_atomic_check()
984 asyh->or.bpc = connector->display_info.bpc; in nv50_msto_atomic_check()
985 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4); in nv50_msto_atomic_check()
988 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr); in nv50_msto_atomic_check()
992 if (!mst_state->pbn_div.full) { in nv50_msto_atomic_check()
993 struct nouveau_encoder *outp = mstc->mstm->outp; in nv50_msto_atomic_check()
995 mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr); in nv50_msto_atomic_check()
998 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); in nv50_msto_atomic_check()
1002 asyh->dp.tu = slots; in nv50_msto_atomic_check()
1022 struct nv50_head *head = msto->head; in nv50_msto_atomic_enable()
1024 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base)); in nv50_msto_atomic_enable()
1031 drm_connector_list_iter_begin(encoder->dev, &conn_iter); in nv50_msto_atomic_enable()
1033 if (connector->state->best_encoder == &msto->encoder) { in nv50_msto_atomic_enable()
1035 mstm = mstc->mstm; in nv50_msto_atomic_enable()
1044 if (!mstm->links++) { in nv50_msto_atomic_enable()
1045 nvif_outp_acquire_sor(&mstm->outp->outp, false /*TODO: MST audio... */); in nv50_msto_atomic_enable()
1046 nouveau_dp_train(mstm->outp, true, 0, 0); in nv50_msto_atomic_enable()
1049 if (head->func->display_id) { in nv50_msto_atomic_enable()
1050 if (!WARN_ON(nvif_outp_dp_mst_id_get(&mstm->outp->outp, &msto->display_id))) in nv50_msto_atomic_enable()
1051 head->func->display_id(head, msto->display_id); in nv50_msto_atomic_enable()
1054 if (mstm->outp->outp.or.link & 1) in nv50_msto_atomic_enable()
1059 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, in nv50_msto_atomic_enable()
1060 nv50_dp_bpc_to_depth(asyh->or.bpc)); in nv50_msto_atomic_enable()
1062 msto->mstc = mstc; in nv50_msto_atomic_enable()
1063 msto->enabled = true; in nv50_msto_atomic_enable()
1064 mstm->modified = true; in nv50_msto_atomic_enable()
1071 struct nv50_mstc *mstc = msto->mstc; in nv50_msto_atomic_disable()
1072 struct nv50_mstm *mstm = mstc->mstm; in nv50_msto_atomic_disable()
1074 if (msto->head->func->display_id) in nv50_msto_atomic_disable()
1075 msto->head->func->display_id(msto->head, 0); in nv50_msto_atomic_disable()
1077 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); in nv50_msto_atomic_disable()
1078 mstm->modified = true; in nv50_msto_atomic_disable()
1079 if (!--mstm->links) in nv50_msto_atomic_disable()
1080 mstm->disabled = true; in nv50_msto_atomic_disable()
1081 msto->disabled = true; in nv50_msto_atomic_disable()
1095 drm_encoder_cleanup(&msto->encoder); in nv50_msto_destroy()
1112 return ERR_PTR(-ENOMEM); in nv50_msto_new()
1114 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, in nv50_msto_new()
1115 DRM_MODE_ENCODER_DPMST, "mst-%d", id); in nv50_msto_new()
1121 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); in nv50_msto_new()
1122 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); in nv50_msto_new()
1123 msto->head = head; in nv50_msto_new()
1134 struct drm_crtc *crtc = connector_state->crtc; in nv50_mstc_atomic_best_encoder()
1136 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) in nv50_mstc_atomic_best_encoder()
1139 return &nv50_head(crtc)->msto->encoder; in nv50_mstc_atomic_best_encoder()
1147 struct nouveau_encoder *outp = mstc->mstm->outp; in nv50_mstc_mode_valid()
1162 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); in nv50_mstc_get_modes()
1163 drm_connector_update_edid_property(&mstc->connector, mstc->edid); in nv50_mstc_get_modes()
1164 if (mstc->edid) in nv50_mstc_get_modes()
1165 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); in nv50_mstc_get_modes()
1173 if (connector->display_info.bpc) in nv50_mstc_get_modes()
1174 connector->display_info.bpc = in nv50_mstc_get_modes()
1175 clamp(connector->display_info.bpc, 6U, 8U); in nv50_mstc_get_modes()
1177 connector->display_info.bpc = 8; in nv50_mstc_get_modes()
1179 if (mstc->native) in nv50_mstc_get_modes()
1180 drm_mode_destroy(mstc->connector.dev, mstc->native); in nv50_mstc_get_modes()
1181 mstc->native = nouveau_conn_native_mode(&mstc->connector); in nv50_mstc_get_modes()
1190 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; in nv50_mstc_atomic_check()
1192 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port); in nv50_mstc_atomic_check()
1205 ret = pm_runtime_get_sync(connector->dev->dev); in nv50_mstc_detect()
1206 if (ret < 0 && ret != -EACCES) { in nv50_mstc_detect()
1207 pm_runtime_put_autosuspend(connector->dev->dev); in nv50_mstc_detect()
1211 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, in nv50_mstc_detect()
1212 mstc->port); in nv50_mstc_detect()
1217 pm_runtime_mark_last_busy(connector->dev->dev); in nv50_mstc_detect()
1218 pm_runtime_put_autosuspend(connector->dev->dev); in nv50_mstc_detect()
1236 drm_connector_cleanup(&mstc->connector); in nv50_mstc_destroy()
1237 drm_dp_mst_put_port_malloc(mstc->port); in nv50_mstc_destroy()
1257 struct drm_device *dev = mstm->outp->base.base.dev; in nv50_mstc_new()
1263 return -ENOMEM; in nv50_mstc_new()
1264 mstc->mstm = mstm; in nv50_mstc_new()
1265 mstc->port = port; in nv50_mstc_new()
1267 ret = drm_connector_dynamic_init(dev, &mstc->connector, &nv50_mstc, in nv50_mstc_new()
1275 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); in nv50_mstc_new()
1277 mstc->connector.funcs->reset(&mstc->connector); in nv50_mstc_new()
1278 nouveau_conn_attach_properties(&mstc->connector); in nv50_mstc_new()
1281 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) in nv50_mstc_new()
1284 drm_connector_attach_encoder(&mstc->connector, in nv50_mstc_new()
1285 &nv50_head(crtc)->msto->encoder); in nv50_mstc_new()
1288 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); in nv50_mstc_new()
1289 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); in nv50_mstc_new()
1290 drm_connector_set_path_property(&mstc->connector, path); in nv50_mstc_new()
1300 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); in nv50_mstm_cleanup()
1303 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); in nv50_mstm_cleanup()
1304 drm_dp_check_act_status(&mstm->mgr); in nv50_mstm_cleanup()
1306 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { in nv50_mstm_cleanup()
1307 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { in nv50_mstm_cleanup()
1309 struct nv50_mstc *mstc = msto->mstc; in nv50_mstm_cleanup()
1310 if (mstc && mstc->mstm == mstm) in nv50_mstm_cleanup()
1311 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto); in nv50_mstm_cleanup()
1315 if (mstm->disabled) { in nv50_mstm_cleanup()
1316 nouveau_dp_power_down(mstm->outp); in nv50_mstm_cleanup()
1317 nvif_outp_release(&mstm->outp->outp); in nv50_mstm_cleanup()
1318 mstm->disabled = false; in nv50_mstm_cleanup()
1321 mstm->modified = false; in nv50_mstm_cleanup()
1329 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); in nv50_mstm_prepare()
1332 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); in nv50_mstm_prepare()
1335 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { in nv50_mstm_prepare()
1336 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { in nv50_mstm_prepare()
1338 struct nv50_mstc *mstc = msto->mstc; in nv50_mstm_prepare()
1339 if (mstc && mstc->mstm == mstm && msto->disabled) in nv50_mstm_prepare()
1340 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); in nv50_mstm_prepare()
1347 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { in nv50_mstm_prepare()
1348 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { in nv50_mstm_prepare()
1350 struct nv50_mstc *mstc = msto->mstc; in nv50_mstm_prepare()
1351 if (mstc && mstc->mstm == mstm && !msto->disabled) in nv50_mstm_prepare()
1352 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); in nv50_mstm_prepare()
1369 return &mstc->connector; in nv50_mstm_add_connector()
1382 struct drm_dp_aux *aux = &nv_connector->aux; in nv50_mstm_service() local
1390 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); in nv50_mstm_service()
1396 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled); in nv50_mstm_service()
1400 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]); in nv50_mstm_service()
1407 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr); in nv50_mstm_service()
1412 nv_connector->base.name, rc); in nv50_mstm_service()
1420 mstm->is_mst = false; in nv50_mstm_remove()
1421 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); in nv50_mstm_remove()
1427 struct nv50_mstm *mstm = outp->dp.mstm; in nv50_mstm_detect()
1428 struct drm_dp_aux *aux; in nv50_mstm_detect() local
1431 if (!mstm || !mstm->can_mst) in nv50_mstm_detect()
1434 aux = mstm->mgr.aux; in nv50_mstm_detect()
1439 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); in nv50_mstm_detect()
1444 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); in nv50_mstm_detect()
1448 mstm->is_mst = true; in nv50_mstm_detect()
1455 struct nv50_mstm *mstm = outp->dp.mstm; in nv50_mstm_fini()
1462 * path to protect mstm->is_mst without potentially deadlocking in nv50_mstm_fini()
1464 mutex_lock(&outp->dp.hpd_irq_lock); in nv50_mstm_fini()
1465 mstm->suspended = true; in nv50_mstm_fini()
1466 mutex_unlock(&outp->dp.hpd_irq_lock); in nv50_mstm_fini()
1468 if (mstm->is_mst) in nv50_mstm_fini()
1469 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); in nv50_mstm_fini()
1475 struct nv50_mstm *mstm = outp->dp.mstm; in nv50_mstm_init()
1481 if (mstm->is_mst) { in nv50_mstm_init()
1482 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); in nv50_mstm_init()
1483 if (ret == -1) in nv50_mstm_init()
1487 mutex_lock(&outp->dp.hpd_irq_lock); in nv50_mstm_init()
1488 mstm->suspended = false; in nv50_mstm_init()
1489 mutex_unlock(&outp->dp.hpd_irq_lock); in nv50_mstm_init()
1491 if (ret == -1) in nv50_mstm_init()
1492 drm_kms_helper_hotplug_event(mstm->mgr.dev); in nv50_mstm_init()
1500 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); in nv50_mstm_del()
1507 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, in nv50_mstm_new() argument
1510 const int max_payloads = hweight8(outp->dcb->heads); in nv50_mstm_new()
1511 struct drm_device *dev = outp->base.base.dev; in nv50_mstm_new()
1516 return -ENOMEM; in nv50_mstm_new()
1517 mstm->outp = outp; in nv50_mstm_new()
1518 mstm->mgr.cbs = &nv50_mstm; in nv50_mstm_new()
1520 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, in nv50_mstm_new()
1535 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); in nv50_sor_update()
1536 struct nv50_core *core = disp->core; in nv50_sor_update()
1539 nv_encoder->ctrl &= ~BIT(head); in nv50_sor_update()
1540 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) in nv50_sor_update()
1541 nv_encoder->ctrl = 0; in nv50_sor_update()
1543 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); in nv50_sor_update()
1544 nv_encoder->ctrl |= BIT(head); in nv50_sor_update()
1545 asyh->or.depth = depth; in nv50_sor_update()
1548 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh); in nv50_sor_update()
1551 /* TODO: Should we extend this to PWM-only backlights?
1560 struct nv50_head *head = nv50_head(nv_encoder->crtc); in nv50_sor_atomic_disable()
1563 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); in nv50_sor_atomic_disable()
1564 struct nouveau_backlight *backlight = nv_connector->backlight; in nv50_sor_atomic_disable()
1565 struct drm_dp_aux *aux = &nv_connector->aux; in nv50_sor_atomic_disable() local
1568 if (backlight && backlight->uses_dpcd) { in nv50_sor_atomic_disable()
1569 ret = drm_edp_backlight_disable(aux, &backlight->edp_info); in nv50_sor_atomic_disable()
1572 nv_connector->base.base.id, nv_connector->base.name, ret); in nv50_sor_atomic_disable()
1576 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS && nv_encoder->hdmi.enabled) { in nv50_sor_atomic_disable()
1577 nvif_outp_hdmi(&nv_encoder->outp, head->base.index, in nv50_sor_atomic_disable()
1579 nv_encoder->hdmi.enabled = false; in nv50_sor_atomic_disable()
1582 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) in nv50_sor_atomic_disable()
1585 if (head->func->display_id) in nv50_sor_atomic_disable()
1586 head->func->display_id(head, 0); in nv50_sor_atomic_disable()
1588 nv_encoder->update(nv_encoder, head->base.index, NULL, 0, 0); in nv50_sor_atomic_disable()
1589 nv50_audio_disable(encoder, &head->base); in nv50_sor_atomic_disable()
1590 nv_encoder->crtc = NULL; in nv50_sor_atomic_disable()
1603 bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP; in nv50_sor_dp_watermark_sst()
1604 u64 minRate = outp->dp.link_bw * 1000; in nv50_sor_dp_watermark_sst()
1616 unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke; in nv50_sor_dp_watermark_sst()
1617 unsigned rasterWidth = asyh->mode.h.active; in nv50_sor_dp_watermark_sst()
1618 unsigned depth = asyh->or.bpc * 3; in nv50_sor_dp_watermark_sst()
1620 u64 pixelClockHz = asyh->mode.clock * 1000; in nv50_sor_dp_watermark_sst()
1622 u32 numLanesPerLink = outp->dp.link_nr; in nv50_sor_dp_watermark_sst()
1630 if (outp->outp.info.dp.increased_wm) { in nv50_sor_dp_watermark_sst()
1635 if ((pixelClockHz * depth) >= (8 * minRate * outp->dp.link_nr * DSC_FACTOR)) in nv50_sor_dp_watermark_sst()
1645 ((pixelClockHz * depth) < div_u64(8 * minRate * outp->dp.link_nr * DSC_FACTOR, 64))) in nv50_sor_dp_watermark_sst()
1657 ratioF = div_u64(ratioF, 8 * (u64) minRate * outp->dp.link_nr); in nv50_sor_dp_watermark_sst()
1662 watermarkF = div_u64(ratioF * tuSize * (PrecisionFactor - ratioF), PrecisionFactor); in nv50_sor_dp_watermark_sst()
1668 numSymbolsPerLine = div_u64(surfaceWidth * depth, 8 * outp->dp.link_nr * DSC_FACTOR); in nv50_sor_dp_watermark_sst()
1691 PixelSteeringBits = remain ? div_u64((numLanesPerLink - remain) * depth, DSC_FACTOR) : 0; in nv50_sor_dp_watermark_sst()
1698 if (WARN_ON(MinHBlank > rasterWidth - surfaceWidth)) in nv50_sor_dp_watermark_sst()
1701 // Bug 702290 - Active Width should be greater than 60 in nv50_sor_dp_watermark_sst()
1706 …hblank_symbols = (s32)(div_u64((u64)(rasterWidth - surfaceWidth - MinHBlank) * minRate, pixelClock… in nv50_sor_dp_watermark_sst()
1709 hblank_symbols -= 1; //Stuffer latency to send BS in nv50_sor_dp_watermark_sst()
1710 hblank_symbols -= 3; //SPKT latency to send data to stuffer in nv50_sor_dp_watermark_sst()
1712 hblank_symbols -= numLanesPerLink == 1 ? 9 : numLanesPerLink == 2 ? 6 : 3; in nv50_sor_dp_watermark_sst()
1717 …nk = ((SetRasterBlankEnd.X + SetRasterSize.Width - SetRasterBlankStart.X - 40) * link_clk / pclk) … in nv50_sor_dp_watermark_sst()
1725 vblank_symbols = (s32)((div_u64((u64)(surfaceWidth - 40) * minRate, pixelClockHz))) - 1; in nv50_sor_dp_watermark_sst()
1727 vblank_symbols -= numLanesPerLink == 1 ? 39 : numLanesPerLink == 2 ? 21 : 12; in nv50_sor_dp_watermark_sst()
1732 return nvif_outp_dp_sst(&outp->outp, head->base.index, waterMark, hBlankSym, vBlankSym); in nv50_sor_dp_watermark_sst()
1741 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); in nv50_sor_atomic_enable()
1742 struct drm_display_mode *mode = &asyh->state.adjusted_mode; in nv50_sor_atomic_enable()
1743 struct nv50_disp *disp = nv50_disp(encoder->dev); in nv50_sor_atomic_enable()
1744 struct nv50_head *head = nv50_head(&nv_crtc->base); in nv50_sor_atomic_enable()
1745 struct nvif_outp *outp = &nv_encoder->outp; in nv50_sor_atomic_enable()
1746 struct drm_device *dev = encoder->dev; in nv50_sor_atomic_enable()
1752 struct nvbios *bios = &drm->vbios; in nv50_sor_atomic_enable()
1758 nv_encoder->crtc = &nv_crtc->base; in nv50_sor_atomic_enable()
1760 if ((disp->disp->object.oclass == GT214_DISP || in nv50_sor_atomic_enable()
1761 disp->disp->object.oclass >= GF110_DISP) && in nv50_sor_atomic_enable()
1762 nv_encoder->dcb->type != DCB_OUTPUT_LVDS && in nv50_sor_atomic_enable()
1763 nv_connector->base.display_info.has_audio) in nv50_sor_atomic_enable()
1769 switch (nv_encoder->dcb->type) { in nv50_sor_atomic_enable()
1771 if (disp->disp->object.oclass != NV50_DISP && in nv50_sor_atomic_enable()
1772 nv_connector->base.display_info.is_hdmi) in nv50_sor_atomic_enable()
1775 if (nv_encoder->outp.or.link & 1) { in nv50_sor_atomic_enable()
1777 /* Only enable dual-link if: in nv50_sor_atomic_enable()
1778 * - Need to (i.e. rate > 165MHz) in nv50_sor_atomic_enable()
1779 * - DCB says we can in nv50_sor_atomic_enable()
1780 * - Not an HDMI monitor, since there's no dual-link in nv50_sor_atomic_enable()
1783 if (mode->clock >= 165000 && in nv50_sor_atomic_enable()
1784 nv_encoder->dcb->duallink_possible && in nv50_sor_atomic_enable()
1785 !nv_connector->base.display_info.is_hdmi) in nv50_sor_atomic_enable()
1794 if (bios->fp_no_ddc) { in nv50_sor_atomic_enable()
1795 lvds_dual = bios->fp.dual_link; in nv50_sor_atomic_enable()
1796 lvds_8bpc = bios->fp.if_is_24bit; in nv50_sor_atomic_enable()
1798 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { in nv50_sor_atomic_enable()
1799 if (((u8 *)nv_connector->edid)[121] == 2) in nv50_sor_atomic_enable()
1802 if (mode->clock >= bios->fp.duallink_transition_clk) { in nv50_sor_atomic_enable()
1807 if (bios->fp.strapless_is_24bit & 2) in nv50_sor_atomic_enable()
1810 if (bios->fp.strapless_is_24bit & 1) in nv50_sor_atomic_enable()
1814 if (asyh->or.bpc == 8) in nv50_sor_atomic_enable()
1818 nvif_outp_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc); in nv50_sor_atomic_enable()
1821 nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc); in nv50_sor_atomic_enable()
1823 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); in nv50_sor_atomic_enable()
1825 if (nv_encoder->outp.or.link & 1) in nv50_sor_atomic_enable()
1831 backlight = nv_connector->backlight; in nv50_sor_atomic_enable()
1832 if (backlight && backlight->uses_dpcd) in nv50_sor_atomic_enable()
1833 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info, in nv50_sor_atomic_enable()
1834 (u16)backlight->dev->props.brightness); in nv50_sor_atomic_enable()
1843 if (head->func->display_id) in nv50_sor_atomic_enable()
1844 head->func->display_id(head, BIT(nv_encoder->outp.id)); in nv50_sor_atomic_enable()
1846 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); in nv50_sor_atomic_enable()
1861 nv50_mstm_del(&nv_encoder->dp.mstm); in nv50_sor_destroy()
1864 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) in nv50_sor_destroy()
1865 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); in nv50_sor_destroy()
1867 nvif_outp_dtor(&nv_encoder->outp); in nv50_sor_destroy()
1879 struct drm_connector *connector = &nv_encoder->conn->base; in nv50_sor_create()
1881 struct nouveau_drm *drm = nouveau_drm(connector->dev); in nv50_sor_create()
1884 struct dcb_output *dcbe = nv_encoder->dcb; in nv50_sor_create()
1885 struct nv50_disp *disp = nv50_disp(connector->dev); in nv50_sor_create()
1888 switch (dcbe->type) { in nv50_sor_create()
1897 nv_encoder->update = nv50_sor_update; in nv50_sor_create()
1900 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, in nv50_sor_create()
1901 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); in nv50_sor_create()
1906 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); in nv50_sor_create()
1909 if (dcbe->type == DCB_OUTPUT_DP) { in nv50_sor_create()
1910 mutex_init(&nv_encoder->dp.hpd_irq_lock); in nv50_sor_create()
1912 if (disp->disp->object.oclass < GF110_DISP) { in nv50_sor_create()
1913 /* HW has no support for address-only in nv50_sor_create()
1915 * use custom I2C-over-AUX code. in nv50_sor_create()
1917 struct nvkm_i2c_aux *aux; in nv50_sor_create() local
1919 aux = nvkm_i2c_aux_find(i2c, dcbe->i2c_index); in nv50_sor_create()
1920 if (!aux) in nv50_sor_create()
1921 return -EINVAL; in nv50_sor_create()
1923 nv_encoder->i2c = &aux->i2c; in nv50_sor_create()
1925 nv_encoder->i2c = &nv_connector->aux.ddc; in nv50_sor_create()
1928 if (nv_connector->type != DCB_CONNECTOR_eDP && nv_encoder->outp.info.dp.mst) { in nv50_sor_create()
1929 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, in nv50_sor_create()
1930 16, nv_connector->base.base.id, in nv50_sor_create()
1931 &nv_encoder->dp.mstm); in nv50_sor_create()
1936 if (nv_encoder->outp.info.ddc != NVIF_OUTP_DDC_INVALID) { in nv50_sor_create()
1937 struct nvkm_i2c_bus *bus = in nv50_sor_create() local
1938 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); in nv50_sor_create()
1939 if (bus) in nv50_sor_create()
1940 nv_encoder->i2c = &bus->i2c; in nv50_sor_create()
1957 crtc_state->adjusted_mode.clock *= 2; in nv50_pior_atomic_check()
1965 struct nv50_core *core = nv50_disp(encoder->dev)->core; in nv50_pior_atomic_disable()
1968 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL); in nv50_pior_atomic_disable()
1969 nv_encoder->crtc = NULL; in nv50_pior_atomic_disable()
1978 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); in nv50_pior_atomic_enable()
1979 struct nv50_core *core = nv50_disp(encoder->dev)->core; in nv50_pior_atomic_enable()
1982 switch (nv_crtc->index) { in nv50_pior_atomic_enable()
1990 switch (asyh->or.bpc) { in nv50_pior_atomic_enable()
1991 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; in nv50_pior_atomic_enable()
1992 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; in nv50_pior_atomic_enable()
1993 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; in nv50_pior_atomic_enable()
1994 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; in nv50_pior_atomic_enable()
1997 if (!nvif_outp_acquired(&nv_encoder->outp)) in nv50_pior_atomic_enable()
1998 nvif_outp_acquire_pior(&nv_encoder->outp); in nv50_pior_atomic_enable()
2000 switch (nv_encoder->dcb->type) { in nv50_pior_atomic_enable()
2006 nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6); in nv50_pior_atomic_enable()
2013 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); in nv50_pior_atomic_enable()
2014 nv_encoder->crtc = &nv_crtc->base; in nv50_pior_atomic_enable()
2029 nvif_outp_dtor(&nv_encoder->outp); in nv50_pior_destroy()
2033 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); in nv50_pior_destroy()
2045 struct drm_connector *connector = &nv_encoder->conn->base; in nv50_pior_create()
2046 struct drm_device *dev = connector->dev; in nv50_pior_create()
2050 struct nvkm_i2c_bus *bus = NULL; in nv50_pior_create() local
2051 struct nvkm_i2c_aux *aux = NULL; in nv50_pior_create() local
2054 struct dcb_output *dcbe = nv_encoder->dcb; in nv50_pior_create()
2057 switch (dcbe->type) { in nv50_pior_create()
2059 bus = nvkm_i2c_bus_find(i2c, nv_encoder->outp.info.ddc); in nv50_pior_create()
2060 ddc = bus ? &bus->i2c : NULL; in nv50_pior_create()
2064 aux = nvkm_i2c_aux_find(i2c, nv_encoder->outp.info.dp.aux); in nv50_pior_create()
2065 ddc = aux ? &aux->i2c : NULL; in nv50_pior_create()
2069 return -ENODEV; in nv50_pior_create()
2072 nv_encoder->i2c = ddc; in nv50_pior_create()
2074 mutex_init(&nv_encoder->dp.hpd_irq_lock); in nv50_pior_create()
2077 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, in nv50_pior_create()
2078 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); in nv50_pior_create()
2083 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); in nv50_pior_create()
2098 struct nouveau_drm *drm = nouveau_drm(state->dev); in nv50_disp_atomic_commit_core()
2099 struct nv50_disp *disp = nv50_disp(drm->dev); in nv50_disp_atomic_commit_core()
2101 struct nv50_core *core = disp->core; in nv50_disp_atomic_commit_core()
2110 if (mstm->modified) in nv50_disp_atomic_commit_core()
2114 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); in nv50_disp_atomic_commit_core()
2115 core->func->update(core, interlock, true); in nv50_disp_atomic_commit_core()
2116 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, in nv50_disp_atomic_commit_core()
2117 disp->core->chan.base.device)) in nv50_disp_atomic_commit_core()
2122 if (mstm->modified) in nv50_disp_atomic_commit_core()
2126 list_for_each_entry(outp, &atom->outp, head) { in nv50_disp_atomic_commit_core()
2127 if (outp->encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { in nv50_disp_atomic_commit_core()
2128 struct nouveau_encoder *nv_encoder = nouveau_encoder(outp->encoder); in nv50_disp_atomic_commit_core()
2130 if (outp->enabled) { in nv50_disp_atomic_commit_core()
2131 nv50_audio_enable(outp->encoder, nouveau_crtc(nv_encoder->crtc), in nv50_disp_atomic_commit_core()
2132 nv_encoder->conn, NULL, NULL); in nv50_disp_atomic_commit_core()
2133 outp->enabled = outp->disabled = false; in nv50_disp_atomic_commit_core()
2135 if (outp->disabled) { in nv50_disp_atomic_commit_core()
2136 nvif_outp_release(&nv_encoder->outp); in nv50_disp_atomic_commit_core()
2137 outp->disabled = false; in nv50_disp_atomic_commit_core()
2153 if (interlock[wndw->interlock.type] & wndw->interlock.data) { in nv50_disp_atomic_commit_wndw()
2154 if (wndw->func->update) in nv50_disp_atomic_commit_wndw()
2155 wndw->func->update(wndw, interlock); in nv50_disp_atomic_commit_wndw()
2163 struct drm_device *dev = state->dev; in nv50_disp_atomic_commit_tail()
2171 struct nv50_core *core = disp->core; in nv50_disp_atomic_commit_tail()
2177 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); in nv50_disp_atomic_commit_tail()
2185 if (atom->lock_core) in nv50_disp_atomic_commit_tail()
2186 mutex_lock(&disp->mutex); in nv50_disp_atomic_commit_tail()
2193 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, in nv50_disp_atomic_commit_tail()
2194 asyh->clr.mask, asyh->set.mask); in nv50_disp_atomic_commit_tail()
2196 if (old_crtc_state->active && !new_crtc_state->active) { in nv50_disp_atomic_commit_tail()
2197 pm_runtime_put_noidle(dev->dev); in nv50_disp_atomic_commit_tail()
2201 if (asyh->clr.mask) { in nv50_disp_atomic_commit_tail()
2202 nv50_head_flush_clr(head, asyh, atom->flush_disable); in nv50_disp_atomic_commit_tail()
2212 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, in nv50_disp_atomic_commit_tail()
2213 asyw->clr.mask, asyw->set.mask); in nv50_disp_atomic_commit_tail()
2214 if (!asyw->clr.mask) in nv50_disp_atomic_commit_tail()
2217 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); in nv50_disp_atomic_commit_tail()
2221 list_for_each_entry(outp, &atom->outp, head) { in nv50_disp_atomic_commit_tail()
2225 encoder = outp->encoder; in nv50_disp_atomic_commit_tail()
2226 help = encoder->helper_private; in nv50_disp_atomic_commit_tail()
2228 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, in nv50_disp_atomic_commit_tail()
2229 outp->clr.mask, outp->set.mask); in nv50_disp_atomic_commit_tail()
2231 if (outp->clr.mask) { in nv50_disp_atomic_commit_tail()
2232 help->atomic_disable(encoder, state); in nv50_disp_atomic_commit_tail()
2233 outp->disabled = true; in nv50_disp_atomic_commit_tail()
2240 if (atom->flush_disable) { in nv50_disp_atomic_commit_tail()
2254 list_for_each_entry(outp, &atom->outp, head) { in nv50_disp_atomic_commit_tail()
2258 encoder = outp->encoder; in nv50_disp_atomic_commit_tail()
2259 help = encoder->helper_private; in nv50_disp_atomic_commit_tail()
2261 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, in nv50_disp_atomic_commit_tail()
2262 outp->set.mask, outp->clr.mask); in nv50_disp_atomic_commit_tail()
2264 if (outp->set.mask) { in nv50_disp_atomic_commit_tail()
2265 help->atomic_enable(encoder, state); in nv50_disp_atomic_commit_tail()
2266 outp->enabled = true; in nv50_disp_atomic_commit_tail()
2276 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, in nv50_disp_atomic_commit_tail()
2277 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
2279 if (asyh->set.mask) { in nv50_disp_atomic_commit_tail()
2284 if (new_crtc_state->active) { in nv50_disp_atomic_commit_tail()
2285 if (!old_crtc_state->active) { in nv50_disp_atomic_commit_tail()
2287 pm_runtime_get_noresume(dev->dev); in nv50_disp_atomic_commit_tail()
2289 if (new_crtc_state->event) in nv50_disp_atomic_commit_tail()
2294 /* Update window->head assignment. in nv50_disp_atomic_commit_tail()
2300 * supports non-fixed mappings). in nv50_disp_atomic_commit_tail()
2302 if (core->assign_windows) { in nv50_disp_atomic_commit_tail()
2303 core->func->wndw.owner(core); in nv50_disp_atomic_commit_tail()
2305 core->assign_windows = false; in nv50_disp_atomic_commit_tail()
2327 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, in nv50_disp_atomic_commit_tail()
2328 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
2330 if (asyh->set.mask) { in nv50_disp_atomic_commit_tail()
2341 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, in nv50_disp_atomic_commit_tail()
2342 asyw->set.mask, asyw->clr.mask); in nv50_disp_atomic_commit_tail()
2343 if ( !asyw->set.mask && in nv50_disp_atomic_commit_tail()
2344 (!asyw->clr.mask || atom->flush_disable)) in nv50_disp_atomic_commit_tail()
2357 !atom->state.legacy_cursor_update) in nv50_disp_atomic_commit_tail()
2360 disp->core->func->update(disp->core, interlock, false); in nv50_disp_atomic_commit_tail()
2363 if (atom->lock_core) in nv50_disp_atomic_commit_tail()
2364 mutex_unlock(&disp->mutex); in nv50_disp_atomic_commit_tail()
2366 list_for_each_entry_safe(outp, outt, &atom->outp, head) { in nv50_disp_atomic_commit_tail()
2367 list_del(&outp->head); in nv50_disp_atomic_commit_tail()
2377 NV_ERROR(drm, "%s: timeout\n", plane->name); in nv50_disp_atomic_commit_tail()
2381 if (new_crtc_state->event) { in nv50_disp_atomic_commit_tail()
2384 if (new_crtc_state->active) in nv50_disp_atomic_commit_tail()
2386 spin_lock_irqsave(&crtc->dev->event_lock, flags); in nv50_disp_atomic_commit_tail()
2387 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); in nv50_disp_atomic_commit_tail()
2388 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in nv50_disp_atomic_commit_tail()
2390 new_crtc_state->event = NULL; in nv50_disp_atomic_commit_tail()
2391 if (new_crtc_state->active) in nv50_disp_atomic_commit_tail()
2406 pm_runtime_mark_last_busy(dev->dev); in nv50_disp_atomic_commit_tail()
2407 pm_runtime_put_autosuspend(dev->dev); in nv50_disp_atomic_commit_tail()
2426 ret = pm_runtime_get_sync(dev->dev); in nv50_disp_atomic_commit()
2427 if (ret < 0 && ret != -EACCES) { in nv50_disp_atomic_commit()
2428 pm_runtime_put_autosuspend(dev->dev); in nv50_disp_atomic_commit()
2436 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); in nv50_disp_atomic_commit()
2456 if (asyw->set.image) in nv50_disp_atomic_commit()
2466 pm_runtime_get_noresume(dev->dev); in nv50_disp_atomic_commit()
2469 queue_work(system_unbound_wq, &state->commit_work); in nv50_disp_atomic_commit()
2477 pm_runtime_put_autosuspend(dev->dev); in nv50_disp_atomic_commit()
2486 list_for_each_entry(outp, &atom->outp, head) { in nv50_disp_outp_atomic_add()
2487 if (outp->encoder == encoder) in nv50_disp_outp_atomic_add()
2493 return ERR_PTR(-ENOMEM); in nv50_disp_outp_atomic_add()
2495 list_add(&outp->head, &atom->outp); in nv50_disp_outp_atomic_add()
2496 outp->encoder = encoder; in nv50_disp_outp_atomic_add()
2504 struct drm_encoder *encoder = old_connector_state->best_encoder; in nv50_disp_outp_atomic_check_clr()
2509 if (!(crtc = old_connector_state->crtc)) in nv50_disp_outp_atomic_check_clr()
2512 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); in nv50_disp_outp_atomic_check_clr()
2513 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); in nv50_disp_outp_atomic_check_clr()
2514 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { in nv50_disp_outp_atomic_check_clr()
2519 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST || in nv50_disp_outp_atomic_check_clr()
2520 nouveau_encoder(outp->encoder)->dcb->type == DCB_OUTPUT_DP) in nv50_disp_outp_atomic_check_clr()
2521 atom->flush_disable = true; in nv50_disp_outp_atomic_check_clr()
2522 outp->clr.ctrl = true; in nv50_disp_outp_atomic_check_clr()
2523 atom->lock_core = true; in nv50_disp_outp_atomic_check_clr()
2533 struct drm_encoder *encoder = connector_state->best_encoder; in nv50_disp_outp_atomic_check_set()
2538 if (!(crtc = connector_state->crtc)) in nv50_disp_outp_atomic_check_set()
2541 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); in nv50_disp_outp_atomic_check_set()
2542 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { in nv50_disp_outp_atomic_check_set()
2547 outp->set.ctrl = true; in nv50_disp_outp_atomic_check_set()
2548 atom->lock_core = true; in nv50_disp_outp_atomic_check_set()
2558 struct nv50_core *core = nv50_disp(dev)->core; in nv50_disp_atomic_check()
2567 if (core->assign_windows && core->func->head->static_wndw_map) { in nv50_disp_atomic_check()
2576 core->func->head->static_wndw_map(head, asyh); in nv50_disp_atomic_check()
2580 /* We need to handle colour management on a per-plane basis. */ in nv50_disp_atomic_check()
2582 if (new_crtc_state->color_mgmt_changed) { in nv50_disp_atomic_check()
2618 list_for_each_entry_safe(outp, outt, &atom->outp, head) { in nv50_disp_atomic_state_clear()
2619 list_del(&outp->head); in nv50_disp_atomic_state_clear()
2630 drm_atomic_state_default_release(&atom->state); in nv50_disp_atomic_state_free()
2639 drm_atomic_state_init(dev, &atom->state) < 0) { in nv50_disp_atomic_state_alloc()
2643 INIT_LIST_HEAD(&atom->outp); in nv50_disp_atomic_state_alloc()
2644 return &atom->state; in nv50_disp_atomic_state_alloc()
2672 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in nv50_display_fini()
2673 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) in nv50_display_fini()
2677 if (!runtime && !drm->headless) in nv50_display_fini()
2678 cancel_work_sync(&drm->hpd_work); in nv50_display_fini()
2689 const u32 encoder_mask = drm_encoder_mask(&outp->base.base); in nv50_display_read_hw_or_state()
2695 switch (outp->dcb->type) { in nv50_display_read_hw_or_state()
2697 ret = nvif_outp_inherit_tmds(&outp->outp, &proto); in nv50_display_read_hw_or_state()
2700 ret = nvif_outp_inherit_dp(&outp->outp, &proto); in nv50_display_read_hw_or_state()
2703 ret = nvif_outp_inherit_lvds(&outp->outp, &proto); in nv50_display_read_hw_or_state()
2706 ret = nvif_outp_inherit_rgb_crt(&outp->outp, &proto); in nv50_display_read_hw_or_state()
2710 outp->base.base.name); in nv50_display_read_hw_or_state()
2721 if (crtc->index != head_idx) in nv50_display_read_hw_or_state()
2724 armh = nv50_head_atom(crtc->state); in nv50_display_read_hw_or_state()
2734 if (nouveau_connector(conn)->index == outp->dcb->connector) { in nv50_display_read_hw_or_state()
2743 armh->state.encoder_mask = encoder_mask; in nv50_display_read_hw_or_state()
2744 armh->state.connector_mask = drm_connector_mask(conn); in nv50_display_read_hw_or_state()
2745 armh->state.active = true; in nv50_display_read_hw_or_state()
2746 armh->state.enable = true; in nv50_display_read_hw_or_state()
2747 pm_runtime_get_noresume(dev->dev); in nv50_display_read_hw_or_state()
2749 outp->crtc = crtc; in nv50_display_read_hw_or_state()
2750 outp->ctrl = NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto) | BIT(crtc->index); in nv50_display_read_hw_or_state()
2753 conn->state->crtc = crtc; in nv50_display_read_hw_or_state()
2754 conn->state->best_encoder = &outp->base.base; in nv50_display_read_hw_or_state()
2761 struct drm_device *dev = drm->dev; in nv50_display_read_hw_state()
2770 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) in nv50_display_read_hw_state()
2782 struct nv50_core *core = nv50_disp(dev)->core; in nv50_display_init()
2786 core->func->init(core); in nv50_display_init()
2788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in nv50_display_init()
2789 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { in nv50_display_init()
2809 nvif_object_unmap(&disp->caps); in nv50_display_destroy()
2810 nvif_object_dtor(&disp->caps); in nv50_display_destroy()
2811 nv50_core_del(&disp->core); in nv50_display_destroy()
2813 nouveau_bo_unmap(disp->sync); in nv50_display_destroy()
2814 if (disp->sync) in nv50_display_destroy()
2815 nouveau_bo_unpin(disp->sync); in nv50_display_destroy()
2816 nouveau_bo_fini(disp->sync); in nv50_display_destroy()
2818 nouveau_display(dev)->priv = NULL; in nv50_display_destroy()
2833 return -ENOMEM; in nv50_display_create()
2835 mutex_init(&disp->mutex); in nv50_display_create()
2837 nouveau_display(dev)->priv = disp; in nv50_display_create()
2838 nouveau_display(dev)->dtor = nv50_display_destroy; in nv50_display_create()
2839 nouveau_display(dev)->init = nv50_display_init; in nv50_display_create()
2840 nouveau_display(dev)->fini = nv50_display_fini; in nv50_display_create()
2841 disp->disp = &nouveau_display(dev)->disp; in nv50_display_create()
2842 dev->mode_config.funcs = &nv50_disp_func; in nv50_display_create()
2843 dev->mode_config.helper_private = &nv50_disp_helper_func; in nv50_display_create()
2844 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; in nv50_display_create()
2845 dev->mode_config.normalize_zpos = true; in nv50_display_create()
2848 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, in nv50_display_create()
2850 0, 0x0000, NULL, NULL, &disp->sync); in nv50_display_create()
2852 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); in nv50_display_create()
2854 ret = nouveau_bo_map(disp->sync); in nv50_display_create()
2856 nouveau_bo_unpin(disp->sync); in nv50_display_create()
2859 nouveau_bo_fini(disp->sync); in nv50_display_create()
2866 ret = nv50_core_new(drm, &disp->core); in nv50_display_create()
2870 disp->core->func->init(disp->core); in nv50_display_create()
2871 if (disp->core->func->caps_init) { in nv50_display_create()
2872 ret = disp->core->func->caps_init(drm, disp); in nv50_display_create()
2878 if (disp->disp->object.oclass >= TU102_DISP) in nv50_display_create()
2879 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; in nv50_display_create()
2881 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) in nv50_display_create()
2882 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; in nv50_display_create()
2884 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; in nv50_display_create()
2891 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using in nv50_display_create()
2894 if (disp->disp->object.oclass >= GM107_DISP) { in nv50_display_create()
2895 dev->mode_config.cursor_width = 256; in nv50_display_create()
2896 dev->mode_config.cursor_height = 256; in nv50_display_create()
2897 } else if (disp->disp->object.oclass >= GK104_DISP) { in nv50_display_create()
2898 dev->mode_config.cursor_width = 128; in nv50_display_create()
2899 dev->mode_config.cursor_height = 128; in nv50_display_create()
2901 dev->mode_config.cursor_width = 64; in nv50_display_create()
2902 dev->mode_config.cursor_height = 64; in nv50_display_create()
2906 for_each_set_bit(i, &disp->disp->outp_mask, sizeof(disp->disp->outp_mask) * 8) { in nv50_display_create()
2913 ret = nvif_outp_ctor(disp->disp, "kmsOutp", i, &outp->outp); in nv50_display_create()
2919 connector = nouveau_connector_create(dev, outp->outp.info.conn); in nv50_display_create()
2921 nvif_outp_dtor(&outp->outp); in nv50_display_create()
2926 outp->base.base.possible_crtcs = outp->outp.info.heads; in nv50_display_create()
2927 outp->base.base.possible_clones = 0; in nv50_display_create()
2928 outp->conn = nouveau_connector(connector); in nv50_display_create()
2930 outp->dcb = kzalloc(sizeof(*outp->dcb), GFP_KERNEL); in nv50_display_create()
2931 if (!outp->dcb) in nv50_display_create()
2934 switch (outp->outp.info.proto) { in nv50_display_create()
2936 outp->dcb->type = DCB_OUTPUT_ANALOG; in nv50_display_create()
2937 outp->dcb->crtconf.maxfreq = outp->outp.info.rgb_crt.freq_max; in nv50_display_create()
2940 outp->dcb->type = DCB_OUTPUT_TMDS; in nv50_display_create()
2941 outp->dcb->duallink_possible = outp->outp.info.tmds.dual; in nv50_display_create()
2944 outp->dcb->type = DCB_OUTPUT_LVDS; in nv50_display_create()
2945 outp->dcb->lvdsconf.use_acpi_for_edid = outp->outp.info.lvds.acpi_edid; in nv50_display_create()
2948 outp->dcb->type = DCB_OUTPUT_DP; in nv50_display_create()
2949 outp->dcb->dpconf.link_nr = outp->outp.info.dp.link_nr; in nv50_display_create()
2950 outp->dcb->dpconf.link_bw = outp->outp.info.dp.link_bw; in nv50_display_create()
2951 if (outp->outp.info.dp.mst) in nv50_display_create()
2959 outp->dcb->heads = outp->outp.info.heads; in nv50_display_create()
2960 outp->dcb->connector = outp->outp.info.conn; in nv50_display_create()
2961 outp->dcb->i2c_index = outp->outp.info.ddc; in nv50_display_create()
2963 switch (outp->outp.info.type) { in nv50_display_create()
2974 i, outp->outp.info.type, outp->outp.info.proto, ret); in nv50_display_create()
2979 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { in nv50_display_create()
2980 if (connector->possible_encoders) in nv50_display_create()
2984 connector->name); in nv50_display_create()
2985 connector->funcs->destroy(connector); in nv50_display_create()
2989 for_each_set_bit(i, &disp->disp->head_mask, sizeof(disp->disp->head_mask) * 8) { in nv50_display_create()
2999 head->msto = nv50_msto_new(dev, head, i); in nv50_display_create()
3000 if (IS_ERR(head->msto)) { in nv50_display_create()
3001 ret = PTR_ERR(head->msto); in nv50_display_create()
3002 head->msto = NULL; in nv50_display_create()
3016 head->msto->encoder.possible_crtcs = disp->disp->head_mask; in nv50_display_create()
3020 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ in nv50_display_create()
3021 dev->vblank_disable_immediate = true; in nv50_display_create()
3036 * Log2(block height) ----------------------------+ *
3037 * Page Kind ----------------------------------+ | *
3038 * Gob Height/Page Kind Generation ------+ | | *
3039 * Sector layout -------+ | | | *
3040 * Compression ------+ | | | | */
3065 * Log2(block height) ----------------------------+ *
3066 * Page Kind ----------------------------------+ | *
3067 * Gob Height/Page Kind Generation ------+ | | *
3068 * Sector layout -------+ | | | *
3069 * Compression ------+ | | | | */