Lines Matching +full:0 +full:x070000
87 if (ret < 0) in nv50_chan_create()
90 while (oclass[0]) { in nv50_chan_create()
91 for (i = 0; i < n; i++) { in nv50_chan_create()
92 if (sclass[i].oclass == oclass[0]) { in nv50_chan_create()
93 ret = nvif_object_ctor(disp, "kmsChan", 0, in nv50_chan_create()
94 oclass[0], data, size, in nv50_chan_create()
96 if (ret == 0) { in nv50_chan_create()
97 ret = nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
145 nvif_wr32(&device->object, 0x070000, 0x00000001); in nv50_dmac_kick()
147 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()
175 if (get == 0) { in nv50_dmac_wind()
177 if (dmac->put == 0) in nv50_dmac_wind()
181 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) in nv50_dmac_wind()
183 ) < 0) in nv50_dmac_wind()
187 PUSH_RSVD(&dmac->push, PUSH_JUMP(&dmac->push, 0)); in nv50_dmac_wind()
188 dmac->cur = 0; in nv50_dmac_wind()
189 return 0; in nv50_dmac_wind()
215 ) < 0) { in nv50_dmac_wait()
224 return 0; in nv50_dmac_wait()
251 if ((nv50_dmac_vram_pushbuf > 0) || in nv50_dmac_create()
252 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) in nv50_dmac_create()
255 ret = nvif_mem_ctor_map(&drm->mmu, "kmsChanPush", type, 0x1000, &dmac->push.mem); in nv50_dmac_create()
264 dmac->max = 0x1000/4 - 1; in nv50_dmac_create()
279 if (syncbuf < 0) in nv50_dmac_create()
280 return 0; in nv50_dmac_create()
287 .start = syncbuf + 0x0000, in nv50_dmac_create()
288 .limit = syncbuf + 0x0fff, in nv50_dmac_create()
299 .start = 0, in nv50_dmac_create()
335 return 0; in nv50_outp_atomic_check_view()
364 return 0; in nv50_outp_atomic_check_view()
417 return 0; in nv50_outp_atomic_check()
490 u32 ctrl = 0; in nv50_dac_atomic_enable()
493 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; in nv50_dac_atomic_enable()
508 asyh->or.depth = 0; in nv50_dac_atomic_enable()
521 if (loadval == 0) in nv50_dac_detect()
525 if (ret <= 0) in nv50_dac_detect()
576 return 0; in nv50_dac_create()
599 int ret = 0; in nv50_audio_component_get_eld()
651 return 0; in nv50_audio_component_bind()
734 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0); in nv50_audio_disable()
775 union hdmi_infoframe infoframe = { 0 }; in nv50_hdmi_enable()
781 } args = { 0 }; in nv50_hdmi_enable()
794 if (ret < 0) { in nv50_hdmi_enable()
806 if (ret < 0) in nv50_hdmi_enable()
807 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", in nv50_hdmi_enable()
818 args.infoframe.version = 0; in nv50_hdmi_enable()
827 size = 0; in nv50_hdmi_enable()
833 memset(&args.data, 0, sizeof(args.data)); in nv50_hdmi_enable()
838 size = 0; in nv50_hdmi_enable()
907 msto->display_id = 0; in nv50_msto_cleanup()
929 int ret = 0; in nv50_msto_prepare()
937 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); in nv50_msto_prepare()
944 if (ret == 0) { in nv50_msto_prepare()
950 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); in nv50_msto_prepare()
974 return 0; in nv50_msto_atomic_check()
999 if (slots < 0) in nv50_msto_atomic_check()
1004 return 0; in nv50_msto_atomic_check()
1046 nouveau_dp_train(mstm->outp, true, 0, 0); in nv50_msto_atomic_enable()
1075 msto->head->func->display_id(msto->head, 0); in nv50_msto_atomic_disable()
1077 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); in nv50_msto_atomic_disable()
1160 int ret = 0; in nv50_mstc_get_modes()
1206 if (ret < 0 && ret != -EACCES) { in nv50_mstc_detect()
1288 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); in nv50_mstc_new()
1289 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); in nv50_mstc_new()
1292 return 0; in nv50_mstc_new()
1432 return 0; in nv50_mstm_detect()
1439 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); in nv50_mstm_detect()
1440 if (ret < 0) in nv50_mstm_detect()
1476 int ret = 0; in nv50_mstm_init()
1525 return 0; in nv50_mstm_new()
1541 nv_encoder->ctrl = 0; in nv50_sor_update()
1570 if (ret < 0) in nv50_sor_atomic_disable()
1578 false, 0, 0, 0, false, false, false); in nv50_sor_atomic_disable()
1586 head->func->display_id(head, 0); in nv50_sor_atomic_disable()
1588 nv_encoder->update(nv_encoder, head->base.index, NULL, 0, 0); in nv50_sor_atomic_disable()
1614 int vblank_symbols = 0; in nv50_sor_dp_watermark_sst()
1642 // 0 active symbols. This may cause HW hang. Bug 200379426 in nv50_sor_dp_watermark_sst()
1681 BlankingBits = 3*8*numLanesPerLink + (enhancedFraming ? 3*8*numLanesPerLink : 0); in nv50_sor_dp_watermark_sst()
1691 PixelSteeringBits = remain ? div_u64((numLanesPerLink - remain) * depth, DSC_FACTOR) : 0; in nv50_sor_dp_watermark_sst()
1714 hBlankSym = (hblank_symbols < 0) ? 0 : hblank_symbols; in nv50_sor_dp_watermark_sst()
1721 vblank_symbols = 0; in nv50_sor_dp_watermark_sst()
1730 vBlankSym = (vblank_symbols < 0) ? 0 : vblank_symbols; in nv50_sor_dp_watermark_sst()
1943 return 0; in nv50_sor_create()
1958 return 0; in nv50_pior_atomic_check()
1980 u32 ctrl = 0; in nv50_pior_atomic_enable()
1983 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; in nv50_pior_atomic_enable()
2086 return 0; in nv50_pior_create()
2243 memset(interlock, 0x00, sizeof(interlock)); in nv50_disp_atomic_commit_tail()
2306 interlock[NV50_DISP_INTERLOCK_CORE] = 0; in nv50_disp_atomic_commit_tail()
2427 if (ret < 0 && ret != -EACCES) { in nv50_disp_atomic_commit()
2510 return 0; in nv50_disp_outp_atomic_check_clr()
2526 return 0; in nv50_disp_outp_atomic_check_clr()
2539 return 0; in nv50_disp_outp_atomic_check_set()
2551 return 0; in nv50_disp_outp_atomic_check_set()
2609 return 0; in nv50_disp_atomic_check()
2639 drm_atomic_state_init(dev, &atom->state) < 0) { in nv50_disp_atomic_state_alloc()
2715 if (ret < 0) in nv50_display_read_hw_or_state()
2767 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); in nv50_display_read_hw_state()
2799 return 0; in nv50_display_init()
2848 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, in nv50_display_create()
2850 0, 0x0000, NULL, NULL, &disp->sync); in nv50_display_create()
2927 outp->base.base.possible_clones = 0; in nv50_display_create()
3042 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
3043 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
3044 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
3045 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
3046 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
3047 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
3048 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
3049 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
3050 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
3051 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
3052 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
3053 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
3054 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
3055 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
3056 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
3057 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
3058 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
3059 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
3071 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
3072 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
3073 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
3074 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
3075 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
3076 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),