Lines Matching +full:d +full:- +full:link
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
12 #include <linux/phy/phy-dp.h>
46 u64 hactive; /* active h-width */
61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
78 struct msm_dp_link *link; member
103 struct msm_dp_link_info *link) in msm_dp_aux_link_configure() argument
108 values[0] = drm_dp_link_rate_to_bw_code(link->rate); in msm_dp_aux_link_configure()
109 values[1] = link->num_lanes; in msm_dp_aux_link_configure()
111 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) in msm_dp_aux_link_configure()
127 reinit_completion(&ctrl->idle_comp); in msm_dp_ctrl_push_idle()
128 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); in msm_dp_ctrl_push_idle()
130 if (!wait_for_completion_timeout(&ctrl->idle_comp, in msm_dp_ctrl_push_idle()
134 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); in msm_dp_ctrl_push_idle()
140 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl()
142 /* Default-> LSCLK DIV: 1/4 LCLK */ in msm_dp_ctrl_config_ctrl()
145 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_config_ctrl()
152 tbd = msm_dp_link_get_test_bits_depth(ctrl->link, in msm_dp_ctrl_config_ctrl()
153 ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_config_ctrl()
158 config |= ((ctrl->link->link_params.num_lanes - 1) in msm_dp_ctrl_config_ctrl()
170 if (ctrl->panel->psr_cap.version) in msm_dp_ctrl_config_ctrl()
173 msm_dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); in msm_dp_ctrl_config_ctrl()
180 msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog); in msm_dp_ctrl_configure_source_params()
181 msm_dp_catalog_setup_peripheral_flush(ctrl->catalog); in msm_dp_ctrl_configure_source_params()
185 tb = msm_dp_link_get_test_bits_depth(ctrl->link, in msm_dp_ctrl_configure_source_params()
186 ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_configure_source_params()
187 cc = msm_dp_link_get_colorimetry_config(ctrl->link); in msm_dp_ctrl_configure_source_params()
188 msm_dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); in msm_dp_ctrl_configure_source_params()
189 msm_dp_panel_timing_cfg(ctrl->panel); in msm_dp_ctrl_configure_source_params()
285 minus_1 = drm_fixp_from_fraction(-1, 1); in _tu_param_compare()
315 int nlanes = in->nlanes; in msm_dp_panel_update_tu_timings()
316 int dsc_num_slices = in->num_of_dsc_slices; in msm_dp_panel_update_tu_timings()
331 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); in msm_dp_panel_update_tu_timings()
332 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); in msm_dp_panel_update_tu_timings()
333 tu->lwidth = in->hactive; in msm_dp_panel_update_tu_timings()
334 tu->hbp_relative_to_pclk = in->hporch; in msm_dp_panel_update_tu_timings()
335 tu->nlanes = in->nlanes; in msm_dp_panel_update_tu_timings()
336 tu->bpp = in->bpp; in msm_dp_panel_update_tu_timings()
337 tu->pixelEnc = in->pixel_enc; in msm_dp_panel_update_tu_timings()
338 tu->dsc_en = in->dsc_en; in msm_dp_panel_update_tu_timings()
339 tu->async_en = in->async_en; in msm_dp_panel_update_tu_timings()
340 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); in msm_dp_panel_update_tu_timings()
341 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); in msm_dp_panel_update_tu_timings()
343 if (tu->pixelEnc == 420) { in msm_dp_panel_update_tu_timings()
345 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); in msm_dp_panel_update_tu_timings()
346 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); in msm_dp_panel_update_tu_timings()
347 tu->hbp_relative_to_pclk_fp = in msm_dp_panel_update_tu_timings()
348 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); in msm_dp_panel_update_tu_timings()
351 if (tu->pixelEnc == 422) { in msm_dp_panel_update_tu_timings()
352 switch (tu->bpp) { in msm_dp_panel_update_tu_timings()
354 tu->bpp = 16; in msm_dp_panel_update_tu_timings()
355 tu->bpc = 8; in msm_dp_panel_update_tu_timings()
358 tu->bpp = 20; in msm_dp_panel_update_tu_timings()
359 tu->bpc = 10; in msm_dp_panel_update_tu_timings()
362 tu->bpp = 16; in msm_dp_panel_update_tu_timings()
363 tu->bpc = 8; in msm_dp_panel_update_tu_timings()
367 tu->bpc = tu->bpp/3; in msm_dp_panel_update_tu_timings()
370 if (!in->dsc_en) in msm_dp_panel_update_tu_timings()
373 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); in msm_dp_panel_update_tu_timings()
374 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); in msm_dp_panel_update_tu_timings()
376 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); in msm_dp_panel_update_tu_timings()
387 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; in msm_dp_panel_update_tu_timings()
390 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); in msm_dp_panel_update_tu_timings()
398 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); in msm_dp_panel_update_tu_timings()
399 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); in msm_dp_panel_update_tu_timings()
402 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); in msm_dp_panel_update_tu_timings()
403 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); in msm_dp_panel_update_tu_timings()
407 tu->pclk_fp = pclk_dsc_fp; in msm_dp_panel_update_tu_timings()
408 tu->lwidth_fp = dwidth_dsc_fp; in msm_dp_panel_update_tu_timings()
409 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; in msm_dp_panel_update_tu_timings()
412 if (in->fec_en) { in msm_dp_panel_update_tu_timings()
414 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); in msm_dp_panel_update_tu_timings()
423 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _tu_valid_boundary_calc()
424 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); in _tu_valid_boundary_calc()
426 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); in _tu_valid_boundary_calc()
428 temp = (tu->i_upper_boundary_count * in _tu_valid_boundary_calc()
429 tu->new_valid_boundary_link + in _tu_valid_boundary_calc()
430 tu->i_lower_boundary_count * in _tu_valid_boundary_calc()
431 (tu->new_valid_boundary_link-1)); in _tu_valid_boundary_calc()
432 tu->average_valid2_fp = drm_fixp_from_fraction(temp, in _tu_valid_boundary_calc()
433 (tu->i_upper_boundary_count + in _tu_valid_boundary_calc()
434 tu->i_lower_boundary_count)); in _tu_valid_boundary_calc()
436 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _tu_valid_boundary_calc()
437 temp2_fp = tu->lwidth_fp; in _tu_valid_boundary_calc()
439 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); in _tu_valid_boundary_calc()
440 tu->n_tus = drm_fixp2int(temp2_fp); in _tu_valid_boundary_calc()
442 tu->n_tus += 1; in _tu_valid_boundary_calc()
444 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); in _tu_valid_boundary_calc()
445 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); in _tu_valid_boundary_calc()
446 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); in _tu_valid_boundary_calc()
447 temp2_fp = temp1_fp - temp2_fp; in _tu_valid_boundary_calc()
448 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); in _tu_valid_boundary_calc()
450 tu->n_remainder_symbols_per_lane_fp = temp2_fp; in _tu_valid_boundary_calc()
452 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _tu_valid_boundary_calc()
453 tu->last_partial_tu_fp = in _tu_valid_boundary_calc()
454 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, in _tu_valid_boundary_calc()
457 if (tu->n_remainder_symbols_per_lane_fp != 0) in _tu_valid_boundary_calc()
458 tu->remainder_symbols_exist = 1; in _tu_valid_boundary_calc()
460 tu->remainder_symbols_exist = 0; in _tu_valid_boundary_calc()
462 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); in _tu_valid_boundary_calc()
463 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); in _tu_valid_boundary_calc()
465 tu->paired_tus = (int)((tu->n_tus_per_lane) / in _tu_valid_boundary_calc()
466 (tu->i_upper_boundary_count + in _tu_valid_boundary_calc()
467 tu->i_lower_boundary_count)); in _tu_valid_boundary_calc()
469 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * in _tu_valid_boundary_calc()
470 (tu->i_upper_boundary_count + in _tu_valid_boundary_calc()
471 tu->i_lower_boundary_count); in _tu_valid_boundary_calc()
473 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { in _tu_valid_boundary_calc()
474 tu->remainder_tus_upper = tu->i_upper_boundary_count; in _tu_valid_boundary_calc()
475 tu->remainder_tus_lower = tu->remainder_tus - in _tu_valid_boundary_calc()
476 tu->i_upper_boundary_count; in _tu_valid_boundary_calc()
478 tu->remainder_tus_upper = tu->remainder_tus; in _tu_valid_boundary_calc()
479 tu->remainder_tus_lower = 0; in _tu_valid_boundary_calc()
482 temp = tu->paired_tus * (tu->i_upper_boundary_count * in _tu_valid_boundary_calc()
483 tu->new_valid_boundary_link + in _tu_valid_boundary_calc()
484 tu->i_lower_boundary_count * in _tu_valid_boundary_calc()
485 (tu->new_valid_boundary_link - 1)) + in _tu_valid_boundary_calc()
486 (tu->remainder_tus_upper * in _tu_valid_boundary_calc()
487 tu->new_valid_boundary_link) + in _tu_valid_boundary_calc()
488 (tu->remainder_tus_lower * in _tu_valid_boundary_calc()
489 (tu->new_valid_boundary_link - 1)); in _tu_valid_boundary_calc()
490 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); in _tu_valid_boundary_calc()
492 if (tu->remainder_symbols_exist) { in _tu_valid_boundary_calc()
493 temp1_fp = tu->total_valid_fp + in _tu_valid_boundary_calc()
494 tu->n_remainder_symbols_per_lane_fp; in _tu_valid_boundary_calc()
495 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); in _tu_valid_boundary_calc()
496 temp2_fp = temp2_fp + tu->last_partial_tu_fp; in _tu_valid_boundary_calc()
499 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); in _tu_valid_boundary_calc()
500 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); in _tu_valid_boundary_calc()
502 tu->effective_valid_fp = temp1_fp; in _tu_valid_boundary_calc()
504 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _tu_valid_boundary_calc()
505 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); in _tu_valid_boundary_calc()
506 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; in _tu_valid_boundary_calc()
508 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _tu_valid_boundary_calc()
509 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); in _tu_valid_boundary_calc()
510 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; in _tu_valid_boundary_calc()
512 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; in _tu_valid_boundary_calc()
514 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _tu_valid_boundary_calc()
515 temp2_fp = tu->lwidth_fp; in _tu_valid_boundary_calc()
517 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); in _tu_valid_boundary_calc()
520 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); in _tu_valid_boundary_calc()
522 tu->n_tus_incl_last_incomplete_tu = 0; in _tu_valid_boundary_calc()
525 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _tu_valid_boundary_calc()
526 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); in _tu_valid_boundary_calc()
527 temp1_fp = tu->average_valid2_fp - temp2_fp; in _tu_valid_boundary_calc()
528 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); in _tu_valid_boundary_calc()
534 temp = tu->i_upper_boundary_count * tu->nlanes; in _tu_valid_boundary_calc()
535 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _tu_valid_boundary_calc()
536 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); in _tu_valid_boundary_calc()
537 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); in _tu_valid_boundary_calc()
538 temp2_fp = temp1_fp - temp2_fp; in _tu_valid_boundary_calc()
546 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); in _tu_valid_boundary_calc()
548 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); in _tu_valid_boundary_calc()
550 tu->extra_required_bytes_new_tmp, 1); in _tu_valid_boundary_calc()
554 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); in _tu_valid_boundary_calc()
556 tu->extra_pclk_cycles_tmp = 0; in _tu_valid_boundary_calc()
558 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); in _tu_valid_boundary_calc()
559 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); in _tu_valid_boundary_calc()
563 tu->extra_pclk_cycles_in_link_clk_tmp = in _tu_valid_boundary_calc()
566 tu->extra_pclk_cycles_in_link_clk_tmp = 0; in _tu_valid_boundary_calc()
568 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; in _tu_valid_boundary_calc()
570 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; in _tu_valid_boundary_calc()
572 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + in _tu_valid_boundary_calc()
573 tu->lower_filler_size_tmp + in _tu_valid_boundary_calc()
574 tu->extra_buffer_margin; in _tu_valid_boundary_calc()
576 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); in _tu_valid_boundary_calc()
577 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); in _tu_valid_boundary_calc()
579 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); in _tu_valid_boundary_calc()
585 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); in _tu_valid_boundary_calc()
591 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, in _tu_valid_boundary_calc()
592 tu->delay_start_time_fp); in _tu_valid_boundary_calc()
598 if (((tu->even_distribution == 1) || in _tu_valid_boundary_calc()
599 ((tu->even_distribution_BF == 0) && in _tu_valid_boundary_calc()
600 (tu->even_distribution_legacy == 0))) && in _tu_valid_boundary_calc()
601 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && in _tu_valid_boundary_calc()
603 (compare_result_1 || (tu->min_hblank_violated == 1)) && in _tu_valid_boundary_calc()
604 (tu->new_valid_boundary_link - 1) > 0 && in _tu_valid_boundary_calc()
606 (tu->delay_start_link_tmp <= 1023)) { in _tu_valid_boundary_calc()
607 tu->upper_boundary_count = tu->i_upper_boundary_count; in _tu_valid_boundary_calc()
608 tu->lower_boundary_count = tu->i_lower_boundary_count; in _tu_valid_boundary_calc()
609 tu->err_fp = tu->n_n_err_fp; in _tu_valid_boundary_calc()
610 tu->boundary_moderation_en = true; in _tu_valid_boundary_calc()
611 tu->tu_size_desired = tu->tu_size; in _tu_valid_boundary_calc()
612 tu->valid_boundary_link = tu->new_valid_boundary_link; in _tu_valid_boundary_calc()
613 tu->effective_valid_recorded_fp = tu->effective_valid_fp; in _tu_valid_boundary_calc()
614 tu->even_distribution_BF = 1; in _tu_valid_boundary_calc()
615 tu->delay_start_link = tu->delay_start_link_tmp; in _tu_valid_boundary_calc()
616 } else if (tu->boundary_mod_lower_err == 0) { in _tu_valid_boundary_calc()
617 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, in _tu_valid_boundary_calc()
618 tu->diff_abs_fp); in _tu_valid_boundary_calc()
620 tu->boundary_mod_lower_err = 1; in _tu_valid_boundary_calc()
649 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ in _dp_ctrl_calc_tu()
652 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); in _dp_ctrl_calc_tu()
653 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); in _dp_ctrl_calc_tu()
654 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); in _dp_ctrl_calc_tu()
656 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _dp_ctrl_calc_tu()
657 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); in _dp_ctrl_calc_tu()
658 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); in _dp_ctrl_calc_tu()
660 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); in _dp_ctrl_calc_tu()
662 tu->original_ratio_fp = tu->ratio_fp; in _dp_ctrl_calc_tu()
663 tu->boundary_moderation_en = false; in _dp_ctrl_calc_tu()
664 tu->upper_boundary_count = 0; in _dp_ctrl_calc_tu()
665 tu->lower_boundary_count = 0; in _dp_ctrl_calc_tu()
666 tu->i_upper_boundary_count = 0; in _dp_ctrl_calc_tu()
667 tu->i_lower_boundary_count = 0; in _dp_ctrl_calc_tu()
668 tu->valid_lower_boundary_link = 0; in _dp_ctrl_calc_tu()
669 tu->even_distribution_BF = 0; in _dp_ctrl_calc_tu()
670 tu->even_distribution_legacy = 0; in _dp_ctrl_calc_tu()
671 tu->even_distribution = 0; in _dp_ctrl_calc_tu()
672 tu->delay_start_time_fp = 0; in _dp_ctrl_calc_tu()
674 tu->err_fp = drm_fixp_from_fraction(1000, 1); in _dp_ctrl_calc_tu()
675 tu->n_err_fp = 0; in _dp_ctrl_calc_tu()
676 tu->n_n_err_fp = 0; in _dp_ctrl_calc_tu()
678 tu->ratio = drm_fixp2int(tu->ratio_fp); in _dp_ctrl_calc_tu()
679 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); in _dp_ctrl_calc_tu()
680 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); in _dp_ctrl_calc_tu()
682 !tu->ratio && tu->dsc_en == 0) { in _dp_ctrl_calc_tu()
683 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); in _dp_ctrl_calc_tu()
684 tu->ratio = drm_fixp2int(tu->ratio_fp); in _dp_ctrl_calc_tu()
685 if (tu->ratio) in _dp_ctrl_calc_tu()
686 tu->ratio_fp = drm_fixp_from_fraction(1, 1); in _dp_ctrl_calc_tu()
689 if (tu->ratio > 1) in _dp_ctrl_calc_tu()
690 tu->ratio = 1; in _dp_ctrl_calc_tu()
692 if (tu->ratio == 1) in _dp_ctrl_calc_tu()
695 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); in _dp_ctrl_calc_tu()
701 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); in _dp_ctrl_calc_tu()
707 if (tu->dsc_en && compare_result_1 && compare_result_2) { in _dp_ctrl_calc_tu()
709 drm_dbg_dp(ctrl->drm_dev, in _dp_ctrl_calc_tu()
710 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN); in _dp_ctrl_calc_tu()
714 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { in _dp_ctrl_calc_tu()
715 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); in _dp_ctrl_calc_tu()
716 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); in _dp_ctrl_calc_tu()
719 tu->n_err_fp = temp1_fp - temp2_fp; in _dp_ctrl_calc_tu()
721 if (tu->n_err_fp < tu->err_fp) { in _dp_ctrl_calc_tu()
722 tu->err_fp = tu->n_err_fp; in _dp_ctrl_calc_tu()
723 tu->tu_size_desired = tu->tu_size; in _dp_ctrl_calc_tu()
727 tu->tu_size_minus1 = tu->tu_size_desired - 1; in _dp_ctrl_calc_tu()
729 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); in _dp_ctrl_calc_tu()
730 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); in _dp_ctrl_calc_tu()
731 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); in _dp_ctrl_calc_tu()
733 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _dp_ctrl_calc_tu()
734 temp2_fp = tu->lwidth_fp; in _dp_ctrl_calc_tu()
737 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); in _dp_ctrl_calc_tu()
739 tu->n_tus = drm_fixp2int(temp2_fp); in _dp_ctrl_calc_tu()
741 tu->n_tus += 1; in _dp_ctrl_calc_tu()
743 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; in _dp_ctrl_calc_tu()
745 drm_dbg_dp(ctrl->drm_dev, in _dp_ctrl_calc_tu()
746 "n_sym = %d, num_of_tus = %d\n", in _dp_ctrl_calc_tu()
747 tu->valid_boundary_link, tu->n_tus); in _dp_ctrl_calc_tu()
749 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); in _dp_ctrl_calc_tu()
750 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); in _dp_ctrl_calc_tu()
751 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); in _dp_ctrl_calc_tu()
752 temp2_fp = temp1_fp - temp2_fp; in _dp_ctrl_calc_tu()
753 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); in _dp_ctrl_calc_tu()
758 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); in _dp_ctrl_calc_tu()
760 tu->extra_bytes = 0; in _dp_ctrl_calc_tu()
762 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); in _dp_ctrl_calc_tu()
763 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); in _dp_ctrl_calc_tu()
767 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); in _dp_ctrl_calc_tu()
769 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); in _dp_ctrl_calc_tu()
771 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); in _dp_ctrl_calc_tu()
772 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); in _dp_ctrl_calc_tu()
776 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); in _dp_ctrl_calc_tu()
778 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); in _dp_ctrl_calc_tu()
780 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; in _dp_ctrl_calc_tu()
782 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); in _dp_ctrl_calc_tu()
783 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); in _dp_ctrl_calc_tu()
785 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + in _dp_ctrl_calc_tu()
786 tu->filler_size + tu->extra_buffer_margin; in _dp_ctrl_calc_tu()
788 tu->resulting_valid_fp = in _dp_ctrl_calc_tu()
789 drm_fixp_from_fraction(tu->valid_boundary_link, 1); in _dp_ctrl_calc_tu()
791 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); in _dp_ctrl_calc_tu()
792 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); in _dp_ctrl_calc_tu()
793 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; in _dp_ctrl_calc_tu()
796 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; in _dp_ctrl_calc_tu()
797 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); in _dp_ctrl_calc_tu()
799 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); in _dp_ctrl_calc_tu()
800 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); in _dp_ctrl_calc_tu()
802 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, in _dp_ctrl_calc_tu()
803 tu->delay_start_time_fp); in _dp_ctrl_calc_tu()
805 tu->min_hblank_violated = 1; in _dp_ctrl_calc_tu()
807 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); in _dp_ctrl_calc_tu()
809 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, in _dp_ctrl_calc_tu()
810 tu->delay_start_time_fp); in _dp_ctrl_calc_tu()
812 tu->min_hblank_violated = 1; in _dp_ctrl_calc_tu()
814 tu->delay_start_time_fp = 0; in _dp_ctrl_calc_tu()
818 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; in _dp_ctrl_calc_tu()
819 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; in _dp_ctrl_calc_tu()
821 temp = drm_fixp2int(tu->diff_abs_fp); in _dp_ctrl_calc_tu()
822 if (!temp && tu->diff_abs_fp <= 0xffff) in _dp_ctrl_calc_tu()
823 tu->diff_abs_fp = 0; in _dp_ctrl_calc_tu()
825 /* if(diff_abs < 0) diff_abs *= -1 */ in _dp_ctrl_calc_tu()
826 if (tu->diff_abs_fp < 0) in _dp_ctrl_calc_tu()
827 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); in _dp_ctrl_calc_tu()
829 tu->boundary_mod_lower_err = 0; in _dp_ctrl_calc_tu()
830 if ((tu->diff_abs_fp != 0 && in _dp_ctrl_calc_tu()
831 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || in _dp_ctrl_calc_tu()
832 (tu->even_distribution_legacy == 0) || in _dp_ctrl_calc_tu()
834 (tu->min_hblank_violated == 1)) { in _dp_ctrl_calc_tu()
836 tu->err_fp = drm_fixp_from_fraction(1000, 1); in _dp_ctrl_calc_tu()
838 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); in _dp_ctrl_calc_tu()
840 tu->delay_start_link_extra_pixclk, 1); in _dp_ctrl_calc_tu()
844 tu->extra_buffer_margin = in _dp_ctrl_calc_tu()
847 tu->extra_buffer_margin = 0; in _dp_ctrl_calc_tu()
849 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _dp_ctrl_calc_tu()
850 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); in _dp_ctrl_calc_tu()
853 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); in _dp_ctrl_calc_tu()
855 tu->n_symbols = 0; in _dp_ctrl_calc_tu()
857 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { in _dp_ctrl_calc_tu()
858 for (tu->i_upper_boundary_count = 1; in _dp_ctrl_calc_tu()
859 tu->i_upper_boundary_count <= 15; in _dp_ctrl_calc_tu()
860 tu->i_upper_boundary_count++) { in _dp_ctrl_calc_tu()
861 for (tu->i_lower_boundary_count = 1; in _dp_ctrl_calc_tu()
862 tu->i_lower_boundary_count <= 15; in _dp_ctrl_calc_tu()
863 tu->i_lower_boundary_count++) { in _dp_ctrl_calc_tu()
868 tu->delay_start_link_extra_pixclk--; in _dp_ctrl_calc_tu()
869 } while (tu->boundary_moderation_en != true && in _dp_ctrl_calc_tu()
870 tu->boundary_mod_lower_err == 1 && in _dp_ctrl_calc_tu()
871 tu->delay_start_link_extra_pixclk != 0); in _dp_ctrl_calc_tu()
873 if (tu->boundary_moderation_en == true) { in _dp_ctrl_calc_tu()
875 (tu->upper_boundary_count * in _dp_ctrl_calc_tu()
876 tu->valid_boundary_link + in _dp_ctrl_calc_tu()
877 tu->lower_boundary_count * in _dp_ctrl_calc_tu()
878 (tu->valid_boundary_link - 1)), 1); in _dp_ctrl_calc_tu()
880 (tu->upper_boundary_count + in _dp_ctrl_calc_tu()
881 tu->lower_boundary_count), 1); in _dp_ctrl_calc_tu()
882 tu->resulting_valid_fp = in _dp_ctrl_calc_tu()
886 tu->tu_size_desired, 1); in _dp_ctrl_calc_tu()
887 tu->ratio_by_tu_fp = in _dp_ctrl_calc_tu()
888 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); in _dp_ctrl_calc_tu()
890 tu->valid_lower_boundary_link = in _dp_ctrl_calc_tu()
891 tu->valid_boundary_link - 1; in _dp_ctrl_calc_tu()
893 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _dp_ctrl_calc_tu()
894 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); in _dp_ctrl_calc_tu()
896 tu->resulting_valid_fp); in _dp_ctrl_calc_tu()
897 tu->n_tus = drm_fixp2int(temp2_fp); in _dp_ctrl_calc_tu()
899 tu->tu_size_minus1 = tu->tu_size_desired - 1; in _dp_ctrl_calc_tu()
900 tu->even_distribution_BF = 1; in _dp_ctrl_calc_tu()
903 drm_fixp_from_fraction(tu->tu_size_desired, 1); in _dp_ctrl_calc_tu()
905 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); in _dp_ctrl_calc_tu()
906 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; in _dp_ctrl_calc_tu()
910 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); in _dp_ctrl_calc_tu()
917 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); in _dp_ctrl_calc_tu()
918 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); in _dp_ctrl_calc_tu()
919 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); in _dp_ctrl_calc_tu()
925 if (tu->async_en) in _dp_ctrl_calc_tu()
926 tu->delay_start_link += (int)temp; in _dp_ctrl_calc_tu()
928 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); in _dp_ctrl_calc_tu()
929 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); in _dp_ctrl_calc_tu()
932 tu_table->valid_boundary_link = tu->valid_boundary_link; in _dp_ctrl_calc_tu()
933 tu_table->delay_start_link = tu->delay_start_link; in _dp_ctrl_calc_tu()
934 tu_table->boundary_moderation_en = tu->boundary_moderation_en; in _dp_ctrl_calc_tu()
935 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; in _dp_ctrl_calc_tu()
936 tu_table->upper_boundary_count = tu->upper_boundary_count; in _dp_ctrl_calc_tu()
937 tu_table->lower_boundary_count = tu->lower_boundary_count; in _dp_ctrl_calc_tu()
938 tu_table->tu_size_minus1 = tu->tu_size_minus1; in _dp_ctrl_calc_tu()
940 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", in _dp_ctrl_calc_tu()
941 tu_table->valid_boundary_link); in _dp_ctrl_calc_tu()
942 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", in _dp_ctrl_calc_tu()
943 tu_table->delay_start_link); in _dp_ctrl_calc_tu()
944 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", in _dp_ctrl_calc_tu()
945 tu_table->boundary_moderation_en); in _dp_ctrl_calc_tu()
946 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", in _dp_ctrl_calc_tu()
947 tu_table->valid_lower_boundary_link); in _dp_ctrl_calc_tu()
948 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", in _dp_ctrl_calc_tu()
949 tu_table->upper_boundary_count); in _dp_ctrl_calc_tu()
950 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", in _dp_ctrl_calc_tu()
951 tu_table->lower_boundary_count); in _dp_ctrl_calc_tu()
952 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", in _dp_ctrl_calc_tu()
953 tu_table->tu_size_minus1); in _dp_ctrl_calc_tu()
964 drm_mode = &ctrl->panel->msm_dp_mode.drm_mode; in msm_dp_ctrl_calc_tu_parameters()
966 in.lclk = ctrl->link->link_params.rate / 1000; in msm_dp_ctrl_calc_tu_parameters()
967 in.pclk_khz = drm_mode->clock; in msm_dp_ctrl_calc_tu_parameters()
968 in.hactive = drm_mode->hdisplay; in msm_dp_ctrl_calc_tu_parameters()
969 in.hporch = drm_mode->htotal - drm_mode->hdisplay; in msm_dp_ctrl_calc_tu_parameters()
970 in.nlanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_calc_tu_parameters()
971 in.bpp = ctrl->panel->msm_dp_mode.bpp; in msm_dp_ctrl_calc_tu_parameters()
972 in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; in msm_dp_ctrl_calc_tu_parameters()
1005 msm_dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, in msm_dp_ctrl_setup_tr_unit()
1013 if (!wait_for_completion_timeout(&ctrl->video_comp, in msm_dp_ctrl_wait4video_ready()
1016 ret = -ETIMEDOUT; in msm_dp_ctrl_wait4video_ready()
1024 union phy_configure_opts *phy_opts = &ctrl->phy_opts; in msm_dp_ctrl_set_vx_px()
1027 phy_opts->dp.voltage[0] = v_level; in msm_dp_ctrl_set_vx_px()
1028 phy_opts->dp.pre[0] = p_level; in msm_dp_ctrl_set_vx_px()
1029 phy_opts->dp.set_voltages = 1; in msm_dp_ctrl_set_vx_px()
1030 phy_configure(ctrl->phy, phy_opts); in msm_dp_ctrl_set_vx_px()
1031 phy_opts->dp.set_voltages = 0; in msm_dp_ctrl_set_vx_px()
1038 struct msm_dp_link *link = ctrl->link; in msm_dp_ctrl_update_vx_px() local
1042 u32 voltage_swing_level = link->phy_params.v_level; in msm_dp_ctrl_update_vx_px()
1043 u32 pre_emphasis_level = link->phy_params.p_level; in msm_dp_ctrl_update_vx_px()
1045 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_vx_px()
1046 "voltage level: %d emphasis level: %d\n", in msm_dp_ctrl_update_vx_px()
1055 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_vx_px()
1056 "max. voltage swing level reached %d\n", in msm_dp_ctrl_update_vx_px()
1062 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_vx_px()
1063 "max. pre-emphasis level reached %d\n", in msm_dp_ctrl_update_vx_px()
1070 lane_cnt = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_update_vx_px()
1075 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", in msm_dp_ctrl_update_vx_px()
1077 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, in msm_dp_ctrl_update_vx_px()
1091 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); in msm_dp_ctrl_train_pattern_set()
1098 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); in msm_dp_ctrl_train_pattern_set()
1107 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_read_link_status()
1109 DRM_ERROR("DP link status read failed, err: %d\n", len); in msm_dp_ctrl_read_link_status()
1110 ret = -EINVAL; in msm_dp_ctrl_read_link_status()
1123 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); in msm_dp_ctrl_link_train_1()
1127 ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); in msm_dp_ctrl_link_train_1()
1138 old_v_level = ctrl->link->phy_params.v_level; in msm_dp_ctrl_link_train_1()
1140 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); in msm_dp_ctrl_link_train_1()
1147 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_1()
1151 if (ctrl->link->phy_params.v_level >= in msm_dp_ctrl_link_train_1()
1154 return -EAGAIN; in msm_dp_ctrl_link_train_1()
1157 if (old_v_level != ctrl->link->phy_params.v_level) { in msm_dp_ctrl_link_train_1()
1159 old_v_level = ctrl->link->phy_params.v_level; in msm_dp_ctrl_link_train_1()
1162 msm_dp_link_adjust_levels(ctrl->link, link_status); in msm_dp_ctrl_link_train_1()
1169 return -ETIMEDOUT; in msm_dp_ctrl_link_train_1()
1176 switch (ctrl->link->link_params.rate) { in msm_dp_ctrl_link_rate_down_shift()
1178 ctrl->link->link_params.rate = 540000; in msm_dp_ctrl_link_rate_down_shift()
1181 ctrl->link->link_params.rate = 270000; in msm_dp_ctrl_link_rate_down_shift()
1184 ctrl->link->link_params.rate = 162000; in msm_dp_ctrl_link_rate_down_shift()
1188 ret = -EINVAL; in msm_dp_ctrl_link_rate_down_shift()
1193 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", in msm_dp_ctrl_link_rate_down_shift()
1194 ctrl->link->link_params.rate); in msm_dp_ctrl_link_rate_down_shift()
1203 if (ctrl->link->link_params.num_lanes == 1) in msm_dp_ctrl_link_lane_down_shift()
1204 return -1; in msm_dp_ctrl_link_lane_down_shift()
1206 ctrl->link->link_params.num_lanes /= 2; in msm_dp_ctrl_link_lane_down_shift()
1207 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; in msm_dp_ctrl_link_lane_down_shift()
1209 ctrl->link->phy_params.p_level = 0; in msm_dp_ctrl_link_lane_down_shift()
1210 ctrl->link->phy_params.v_level = 0; in msm_dp_ctrl_link_lane_down_shift()
1218 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in msm_dp_ctrl_clear_training_pattern()
1230 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); in msm_dp_ctrl_link_train_2()
1234 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1237 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1245 ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); in msm_dp_ctrl_link_train_2()
1252 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in msm_dp_ctrl_link_train_2()
1259 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_2()
1263 msm_dp_link_adjust_levels(ctrl->link, link_status); in msm_dp_ctrl_link_train_2()
1270 return -ETIMEDOUT; in msm_dp_ctrl_link_train_2()
1277 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train()
1284 link_info.num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_link_train()
1285 link_info.rate = ctrl->link->link_params.rate; in msm_dp_ctrl_link_train()
1288 msm_dp_link_reset_phy_params_vx_px(ctrl->link); in msm_dp_ctrl_link_train()
1290 msm_dp_aux_link_configure(ctrl->aux, &link_info); in msm_dp_ctrl_link_train()
1296 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); in msm_dp_ctrl_link_train()
1300 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, in msm_dp_ctrl_link_train()
1306 DRM_ERROR("link training #1 failed. ret=%d\n", ret); in msm_dp_ctrl_link_train()
1311 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n"); in msm_dp_ctrl_link_train()
1315 DRM_ERROR("link training #2 failed. ret=%d\n", ret); in msm_dp_ctrl_link_train()
1320 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n"); in msm_dp_ctrl_link_train()
1323 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); in msm_dp_ctrl_link_train()
1333 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); in msm_dp_ctrl_setup_main_link()
1335 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) in msm_dp_ctrl_setup_main_link()
1341 * a link training pattern, we have to first do soft reset. in msm_dp_ctrl_setup_main_link()
1356 if (ctrl->core_clks_on) { in msm_dp_ctrl_core_clk_enable()
1357 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); in msm_dp_ctrl_core_clk_enable()
1361 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_core_clk_enable()
1365 ctrl->core_clks_on = true; in msm_dp_ctrl_core_clk_enable()
1367 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); in msm_dp_ctrl_core_clk_enable()
1368 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_core_clk_enable()
1369 ctrl->stream_clks_on ? "on" : "off", in msm_dp_ctrl_core_clk_enable()
1370 ctrl->link_clks_on ? "on" : "off", in msm_dp_ctrl_core_clk_enable()
1371 ctrl->core_clks_on ? "on" : "off"); in msm_dp_ctrl_core_clk_enable()
1382 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_core_clk_disable()
1384 ctrl->core_clks_on = false; in msm_dp_ctrl_core_clk_disable()
1386 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); in msm_dp_ctrl_core_clk_disable()
1387 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_core_clk_disable()
1388 ctrl->stream_clks_on ? "on" : "off", in msm_dp_ctrl_core_clk_disable()
1389 ctrl->link_clks_on ? "on" : "off", in msm_dp_ctrl_core_clk_disable()
1390 ctrl->core_clks_on ? "on" : "off"); in msm_dp_ctrl_core_clk_disable()
1400 if (ctrl->link_clks_on) { in msm_dp_ctrl_link_clk_enable()
1401 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); in msm_dp_ctrl_link_clk_enable()
1405 if (!ctrl->core_clks_on) { in msm_dp_ctrl_link_clk_enable()
1406 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); in msm_dp_ctrl_link_clk_enable()
1411 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_link_clk_enable()
1415 ctrl->link_clks_on = true; in msm_dp_ctrl_link_clk_enable()
1417 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); in msm_dp_ctrl_link_clk_enable()
1418 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_link_clk_enable()
1419 ctrl->stream_clks_on ? "on" : "off", in msm_dp_ctrl_link_clk_enable()
1420 ctrl->link_clks_on ? "on" : "off", in msm_dp_ctrl_link_clk_enable()
1421 ctrl->core_clks_on ? "on" : "off"); in msm_dp_ctrl_link_clk_enable()
1432 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_link_clk_disable()
1434 ctrl->link_clks_on = false; in msm_dp_ctrl_link_clk_disable()
1436 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); in msm_dp_ctrl_link_clk_disable()
1437 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_link_clk_disable()
1438 ctrl->stream_clks_on ? "on" : "off", in msm_dp_ctrl_link_clk_disable()
1439 ctrl->link_clks_on ? "on" : "off", in msm_dp_ctrl_link_clk_disable()
1440 ctrl->core_clks_on ? "on" : "off"); in msm_dp_ctrl_link_clk_disable()
1446 struct phy *phy = ctrl->phy; in msm_dp_ctrl_enable_mainlink_clocks()
1447 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_enable_mainlink_clocks()
1449 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_enable_mainlink_clocks()
1450 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; in msm_dp_ctrl_enable_mainlink_clocks()
1451 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); in msm_dp_ctrl_enable_mainlink_clocks()
1453 phy_configure(phy, &ctrl->phy_opts); in msm_dp_ctrl_enable_mainlink_clocks()
1456 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); in msm_dp_ctrl_enable_mainlink_clocks()
1457 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_enable_mainlink_clocks()
1459 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); in msm_dp_ctrl_enable_mainlink_clocks()
1461 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); in msm_dp_ctrl_enable_mainlink_clocks()
1472 msm_dp_catalog_ctrl_reset(ctrl->catalog); in msm_dp_ctrl_reset_irq_ctrl()
1480 msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); in msm_dp_ctrl_reset_irq_ctrl()
1489 if (!ctrl->panel->psr_cap.version) in msm_dp_ctrl_config_psr()
1492 msm_dp_catalog_ctrl_config_psr(ctrl->catalog); in msm_dp_ctrl_config_psr()
1495 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); in msm_dp_ctrl_config_psr()
1503 if (!ctrl->panel->psr_cap.version) in msm_dp_ctrl_set_psr()
1517 reinit_completion(&ctrl->psr_op_comp); in msm_dp_ctrl_set_psr()
1518 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, true); in msm_dp_ctrl_set_psr()
1520 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, in msm_dp_ctrl_set_psr()
1523 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); in msm_dp_ctrl_set_psr()
1528 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); in msm_dp_ctrl_set_psr()
1530 msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); in msm_dp_ctrl_set_psr()
1532 msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); in msm_dp_ctrl_set_psr()
1534 msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); in msm_dp_ctrl_set_psr()
1535 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_set_psr()
1537 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); in msm_dp_ctrl_set_psr()
1547 phy = ctrl->phy; in msm_dp_ctrl_phy_init()
1549 msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); in msm_dp_ctrl_phy_init()
1552 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_phy_init()
1553 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_phy_init()
1562 phy = ctrl->phy; in msm_dp_ctrl_phy_exit()
1564 msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); in msm_dp_ctrl_phy_exit()
1566 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_phy_exit()
1567 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_phy_exit()
1572 struct phy *phy = ctrl->phy; in msm_dp_ctrl_reinitialize_mainlink()
1575 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); in msm_dp_ctrl_reinitialize_mainlink()
1576 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_reinitialize_mainlink()
1577 phy_configure(phy, &ctrl->phy_opts); in msm_dp_ctrl_reinitialize_mainlink()
1579 * Disable and re-enable the mainlink clock since the in msm_dp_ctrl_reinitialize_mainlink()
1580 * link clock might have been adjusted as part of the in msm_dp_ctrl_reinitialize_mainlink()
1581 * link maintenance. in msm_dp_ctrl_reinitialize_mainlink()
1583 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_reinitialize_mainlink()
1585 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1588 /* hw recommended delay before re-enabling clocks */ in msm_dp_ctrl_reinitialize_mainlink()
1593 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); in msm_dp_ctrl_reinitialize_mainlink()
1604 phy = ctrl->phy; in msm_dp_ctrl_deinitialize_mainlink()
1606 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); in msm_dp_ctrl_deinitialize_mainlink()
1608 msm_dp_catalog_ctrl_reset(ctrl->catalog); in msm_dp_ctrl_deinitialize_mainlink()
1610 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_deinitialize_mainlink()
1611 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1619 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_deinitialize_mainlink()
1620 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_deinitialize_mainlink()
1629 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_link_maintenance()
1631 ctrl->link->phy_params.p_level = 0; in msm_dp_ctrl_link_maintenance()
1632 ctrl->link->phy_params.v_level = 0; in msm_dp_ctrl_link_maintenance()
1640 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_link_maintenance()
1651 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; in msm_dp_ctrl_send_phy_test_pattern()
1653 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); in msm_dp_ctrl_send_phy_test_pattern()
1656 ctrl->link->phy_params.v_level, in msm_dp_ctrl_send_phy_test_pattern()
1657 ctrl->link->phy_params.p_level)) { in msm_dp_ctrl_send_phy_test_pattern()
1661 msm_dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); in msm_dp_ctrl_send_phy_test_pattern()
1663 msm_dp_link_send_test_response(ctrl->link); in msm_dp_ctrl_send_phy_test_pattern()
1665 pattern_sent = msm_dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); in msm_dp_ctrl_send_phy_test_pattern()
1694 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", in msm_dp_ctrl_send_phy_test_pattern()
1704 if (!ctrl->link->phy_params.phy_test_pattern_sel) { in msm_dp_ctrl_process_phy_test_request()
1705 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_process_phy_test_request()
1711 * The global reset will need DP link related clocks to be in msm_dp_ctrl_process_phy_test_request()
1713 * link clocks and core clocks. in msm_dp_ctrl_process_phy_test_request()
1715 msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_process_phy_test_request()
1717 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_process_phy_test_request()
1719 DRM_ERROR("failed to enable DP link controller\n"); in msm_dp_ctrl_process_phy_test_request()
1723 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_process_phy_test_request()
1724 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_process_phy_test_request()
1726 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); in msm_dp_ctrl_process_phy_test_request()
1730 if (ctrl->stream_clks_on) { in msm_dp_ctrl_process_phy_test_request()
1731 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); in msm_dp_ctrl_process_phy_test_request()
1733 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_process_phy_test_request()
1735 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); in msm_dp_ctrl_process_phy_test_request()
1738 ctrl->stream_clks_on = true; in msm_dp_ctrl_process_phy_test_request()
1757 sink_request = ctrl->link->sink_request; in msm_dp_ctrl_handle_sink_request()
1760 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); in msm_dp_ctrl_handle_sink_request()
1775 msm_dp_link_send_test_response(ctrl->link); in msm_dp_ctrl_handle_sink_request()
1805 int num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_channel_eq_ok()
1824 return -EINVAL; in msm_dp_ctrl_on_link()
1828 rate = ctrl->panel->link_info.rate; in msm_dp_ctrl_on_link()
1829 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_link()
1831 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_on_link()
1833 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { in msm_dp_ctrl_on_link()
1834 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_link()
1835 "using phy test link parameters\n"); in msm_dp_ctrl_on_link()
1839 ctrl->link->link_params.rate = rate; in msm_dp_ctrl_on_link()
1840 ctrl->link->link_params.num_lanes = in msm_dp_ctrl_on_link()
1841 ctrl->panel->link_info.num_lanes; in msm_dp_ctrl_on_link()
1842 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_on_link()
1846 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", in msm_dp_ctrl_on_link()
1847 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, in msm_dp_ctrl_on_link()
1854 while (--link_train_max_retries) { in msm_dp_ctrl_on_link()
1861 /* link train_1 failed */ in msm_dp_ctrl_on_link()
1862 if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) in msm_dp_ctrl_on_link()
1870 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_on_link()
1886 /* link train_2 failed */ in msm_dp_ctrl_on_link()
1887 if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) in msm_dp_ctrl_on_link()
1893 ctrl->link->link_params.num_lanes)) in msm_dp_ctrl_on_link()
1903 /* stop link training before start re training */ in msm_dp_ctrl_on_link()
1909 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc); in msm_dp_ctrl_on_link()
1914 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) in msm_dp_ctrl_on_link()
1917 if (rc == 0) { /* link train successfully */ in msm_dp_ctrl_on_link()
1920 * stop link training at on_stream in msm_dp_ctrl_on_link()
1925 * link training failed in msm_dp_ctrl_on_link()
1931 rc = -ECONNRESET; in msm_dp_ctrl_on_link()
1953 return -EINVAL; in msm_dp_ctrl_on_stream()
1957 pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_stream()
1959 if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_on_stream()
1962 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", in msm_dp_ctrl_on_stream()
1963 ctrl->link->link_params.rate, in msm_dp_ctrl_on_stream()
1964 ctrl->link->link_params.num_lanes, pixel_rate); in msm_dp_ctrl_on_stream()
1966 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_stream()
1967 "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", in msm_dp_ctrl_on_stream()
1968 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); in msm_dp_ctrl_on_stream()
1970 if (!ctrl->link_clks_on) { /* link clk is off */ in msm_dp_ctrl_on_stream()
1973 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); in msm_dp_ctrl_on_stream()
1978 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_on_stream()
1980 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); in msm_dp_ctrl_on_stream()
1984 if (ctrl->stream_clks_on) { in msm_dp_ctrl_on_stream()
1985 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); in msm_dp_ctrl_on_stream()
1987 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_on_stream()
1989 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); in msm_dp_ctrl_on_stream()
1992 ctrl->stream_clks_on = true; in msm_dp_ctrl_on_stream()
1998 /* stop txing train pattern to end link training */ in msm_dp_ctrl_on_stream()
2005 reinit_completion(&ctrl->video_comp); in msm_dp_ctrl_on_stream()
2009 msm_dp_catalog_ctrl_config_msa(ctrl->catalog, in msm_dp_ctrl_on_stream()
2010 ctrl->link->link_params.rate, in msm_dp_ctrl_on_stream()
2012 ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); in msm_dp_ctrl_on_stream()
2016 msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_on_stream()
2022 mainlink_ready = msm_dp_catalog_ctrl_mainlink_ready(ctrl->catalog); in msm_dp_ctrl_on_stream()
2023 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_stream()
2036 phy = ctrl->phy; in msm_dp_ctrl_off_link_stream()
2038 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); in msm_dp_ctrl_off_link_stream()
2041 msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); in msm_dp_ctrl_off_link_stream()
2043 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); in msm_dp_ctrl_off_link_stream()
2045 if (ctrl->stream_clks_on) { in msm_dp_ctrl_off_link_stream()
2046 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off_link_stream()
2047 ctrl->stream_clks_on = false; in msm_dp_ctrl_off_link_stream()
2050 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off_link_stream()
2051 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off_link_stream()
2059 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_off_link_stream()
2060 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_off_link_stream()
2069 phy = ctrl->phy; in msm_dp_ctrl_off_link()
2071 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); in msm_dp_ctrl_off_link()
2073 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off_link()
2074 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off_link()
2076 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", in msm_dp_ctrl_off_link()
2077 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_off_link()
2081 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n", in msm_dp_ctrl_off_link()
2082 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_off_link()
2091 phy = ctrl->phy; in msm_dp_ctrl_off()
2093 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); in msm_dp_ctrl_off()
2095 msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); in msm_dp_ctrl_off()
2097 msm_dp_catalog_ctrl_reset(ctrl->catalog); in msm_dp_ctrl_off()
2099 if (ctrl->stream_clks_on) { in msm_dp_ctrl_off()
2100 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off()
2101 ctrl->stream_clks_on = false; in msm_dp_ctrl_off()
2104 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off()
2105 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off()
2108 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_off()
2109 phy, phy->init_count, phy->power_count); in msm_dp_ctrl_off()
2123 if (ctrl->panel->psr_cap.version) { in msm_dp_ctrl_isr()
2124 isr = msm_dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); in msm_dp_ctrl_isr()
2127 complete(&ctrl->psr_op_comp); in msm_dp_ctrl_isr()
2130 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n"); in msm_dp_ctrl_isr()
2133 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n"); in msm_dp_ctrl_isr()
2136 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); in msm_dp_ctrl_isr()
2139 isr = msm_dp_catalog_ctrl_get_interrupt(ctrl->catalog); in msm_dp_ctrl_isr()
2143 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); in msm_dp_ctrl_isr()
2144 complete(&ctrl->video_comp); in msm_dp_ctrl_isr()
2149 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); in msm_dp_ctrl_isr()
2150 complete(&ctrl->idle_comp); in msm_dp_ctrl_isr()
2174 dev = ctrl->dev; in msm_dp_ctrl_clk_init()
2176 ctrl->num_core_clks = ARRAY_SIZE(core_clks); in msm_dp_ctrl_clk_init()
2177 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); in msm_dp_ctrl_clk_init()
2178 if (!ctrl->core_clks) in msm_dp_ctrl_clk_init()
2179 return -ENOMEM; in msm_dp_ctrl_clk_init()
2181 for (i = 0; i < ctrl->num_core_clks; i++) in msm_dp_ctrl_clk_init()
2182 ctrl->core_clks[i].id = core_clks[i]; in msm_dp_ctrl_clk_init()
2184 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_clk_init()
2188 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); in msm_dp_ctrl_clk_init()
2189 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); in msm_dp_ctrl_clk_init()
2190 if (!ctrl->link_clks) in msm_dp_ctrl_clk_init()
2191 return -ENOMEM; in msm_dp_ctrl_clk_init()
2193 for (i = 0; i < ctrl->num_link_clks; i++) in msm_dp_ctrl_clk_init()
2194 ctrl->link_clks[i].id = ctrl_clks[i]; in msm_dp_ctrl_clk_init()
2196 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_clk_init()
2200 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); in msm_dp_ctrl_clk_init()
2201 if (IS_ERR(ctrl->pixel_clk)) in msm_dp_ctrl_clk_init()
2202 return PTR_ERR(ctrl->pixel_clk); in msm_dp_ctrl_clk_init()
2207 struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, in msm_dp_ctrl_get() argument
2216 !link || !catalog) { in msm_dp_ctrl_get()
2218 return ERR_PTR(-EINVAL); in msm_dp_ctrl_get()
2224 return ERR_PTR(-ENOMEM); in msm_dp_ctrl_get()
2239 init_completion(&ctrl->idle_comp); in msm_dp_ctrl_get()
2240 init_completion(&ctrl->psr_op_comp); in msm_dp_ctrl_get()
2241 init_completion(&ctrl->video_comp); in msm_dp_ctrl_get()
2244 ctrl->panel = panel; in msm_dp_ctrl_get()
2245 ctrl->aux = aux; in msm_dp_ctrl_get()
2246 ctrl->link = link; in msm_dp_ctrl_get()
2247 ctrl->catalog = catalog; in msm_dp_ctrl_get()
2248 ctrl->dev = dev; in msm_dp_ctrl_get()
2249 ctrl->phy = phy; in msm_dp_ctrl_get()
2251 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_get()
2257 return &ctrl->msm_dp_ctrl; in msm_dp_ctrl_get()