1 /* SPDX-License-Identifier: GPL-2.0-only */
33  * @enum adreno_family: identify generation and possibly sub-generation
35  * In some cases there are distinct sub-generations within a major revision
37  * necessary sub-generation.
91 	 * @chipids: Table of matching chip-ids
133  *      -----+---------
186 	 * of gpu firmware to linux-firmware, the fw files were
188 	 * android kernel.  But linux-firmware preferred they be
240 		 * Whether to use 4-channel macrotiling mode or the newer
241 		 * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
242 		 * 4-channel and 1 is 8-channel.
276 	int __ret = -ETIMEDOUT;                            \
293 	WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);  in adreno_patchid()
294 	return gpu->chip_id & 0xff;  in adreno_patchid()
299 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_revn()
301 	return gpu->info->revn == revn;  in adreno_is_revn()
306 	return gpu->gmu_is_wrapper;  in adreno_has_gmu_wrapper()
311 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a2xx()
313 	return gpu->info->family <= ADRENO_2XX_GEN2;  in adreno_is_a2xx()
318 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a20x()
320 	return gpu->info->family == ADRENO_2XX_GEN1;  in adreno_is_a20x()
335 	return gpu->info->chip_ids[0] == 0x03000512;  in adreno_is_a305b()
442 	return gpu->info->chip_ids[0] == 0x06020100;  in adreno_is_a621()
447 	return adreno_is_revn(gpu, 630);  in adreno_is_a630()
462 	return gpu->info->chip_ids[0] == 0x06030500;  in adreno_is_7c3()
477 	return gpu->info->chip_ids[0] == 0x06060300;  in adreno_is_a663()
482 	return gpu->info->chip_ids[0] == 0x06090000;  in adreno_is_a690()
487 	return gpu->info->chip_ids[0] == 0x07000200;  in adreno_is_a702()
492 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a610_family()
508 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a630_family()
510 	return gpu->info->family == ADRENO_6XX_GEN1;  in adreno_is_a630_family()
515 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a660_family()
517 	return gpu->info->family == ADRENO_6XX_GEN4;  in adreno_is_a660_family()
523 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a650_family()
525 	return gpu->info->family == ADRENO_6XX_GEN3 ||  in adreno_is_a650_family()
526 	       gpu->info->family == ADRENO_6XX_GEN4;  in adreno_is_a650_family()
531 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a640_family()
533 	return gpu->info->family == ADRENO_6XX_GEN2;  in adreno_is_a640_family()
538 	return gpu->info->chip_ids[0] == 0x07030001;  in adreno_is_a730()
543 	return gpu->info->chip_ids[0] == 0x43050a01;  in adreno_is_a740()
548 	return gpu->info->chip_ids[0] == 0x43051401;  in adreno_is_a750()
553 	return gpu->info->chip_ids[0] == 0x43050c01;  in adreno_is_x185()
558 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a740_family()
560 	return gpu->info->family == ADRENO_7XX_GEN2 ||  in adreno_is_a740_family()
561 	       gpu->info->family == ADRENO_7XX_GEN3;  in adreno_is_a740_family()
566 	return gpu->info->family == ADRENO_7XX_GEN3;  in adreno_is_a750_family()
571 	/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */  in adreno_is_a7xx()
572 	return gpu->info->family == ADRENO_7XX_GEN1 ||  in adreno_is_a7xx()
616  * Common helper function to initialize the default address space for arm-smmu
640 /* ringbuffer helpers (the parts that are adreno specific) */
646 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));  in OUT_PKT0()
649 /* no-op packet: */
661 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));  in OUT_PKT3()
705 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);  in get_wptr()
710  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
716  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
734 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \