Lines Matching +full:0 +full:x10004000
55 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
117 u32 bw_index = 0; in a6xx_gmu_set_freq()
119 int ret = 0; in a6xx_gmu_set_freq()
126 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) in a6xx_gmu_set_freq()
132 unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); in a6xx_gmu_set_freq()
134 for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { in a6xx_gmu_set_freq()
183 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); in a6xx_gmu_set_freq()
186 ((3 & 0xf) << 28) | perf_index); in a6xx_gmu_set_freq()
192 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); in a6xx_gmu_set_freq()
247 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); in a6xx_gmu_start()
248 if (val <= 0x20010004) { in a6xx_gmu_start()
249 mask = 0xffffffff; in a6xx_gmu_start()
250 reset_val = 0xbabeface; in a6xx_gmu_start()
252 mask = 0x1ff; in a6xx_gmu_start()
253 reset_val = 0x100; in a6xx_gmu_start()
262 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); in a6xx_gmu_start()
264 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); in a6xx_gmu_start()
267 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); in a6xx_gmu_start()
372 "Timeout waiting for GMU OOB set %s: 0x%x\n", in a6xx_gmu_set_oob()
407 return 0; in a6xx_sptprac_enable()
409 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); in a6xx_sptprac_enable()
412 (val & 0x38) == 0x28, 1, 100); in a6xx_sptprac_enable()
415 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", in a6xx_sptprac_enable()
419 return 0; in a6xx_sptprac_enable()
432 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); in a6xx_sptprac_disable()
434 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); in a6xx_sptprac_disable()
437 (val & 0x04), 100, 10000); in a6xx_sptprac_disable()
440 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", in a6xx_sptprac_disable()
450 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); in a6xx_gmu_gfx_rail_on()
455 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); in a6xx_gmu_gfx_rail_on()
456 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); in a6xx_gmu_gfx_rail_on()
473 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); in a6xx_gemnoc_workaround()
482 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); in a6xx_gmu_notify_slumber()
502 != 0x0f) { in a6xx_gmu_notify_slumber()
512 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_gmu_notify_slumber()
538 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_start()
540 return 0; in a6xx_rpmh_start()
555 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_stop()
584 pdc_address_offset = 0x30090; in a6xx_gmu_rpmh_init()
586 pdc_address_offset = 0x300a0; in a6xx_gmu_rpmh_init()
588 pdc_address_offset = 0x30080; in a6xx_gmu_rpmh_init()
601 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); in a6xx_gmu_rpmh_init()
602 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); in a6xx_gmu_rpmh_init()
603 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); in a6xx_gmu_rpmh_init()
604 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); in a6xx_gmu_rpmh_init()
606 adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000); in a6xx_gmu_rpmh_init()
607 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); in a6xx_gmu_rpmh_init()
608 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); in a6xx_gmu_rpmh_init()
609 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); in a6xx_gmu_rpmh_init()
610 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); in a6xx_gmu_rpmh_init()
611 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); in a6xx_gmu_rpmh_init()
620 gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0); in a6xx_gmu_rpmh_init()
621 gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab); in a6xx_gmu_rpmh_init()
622 gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581); in a6xx_gmu_rpmh_init()
623 gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2); in a6xx_gmu_rpmh_init()
624 gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad); in a6xx_gmu_rpmh_init()
626 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); in a6xx_gmu_rpmh_init()
627 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); in a6xx_gmu_rpmh_init()
628 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); in a6xx_gmu_rpmh_init()
629 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); in a6xx_gmu_rpmh_init()
630 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); in a6xx_gmu_rpmh_init()
637 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); in a6xx_gmu_rpmh_init()
638 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); in a6xx_gmu_rpmh_init()
639 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); in a6xx_gmu_rpmh_init()
640 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); in a6xx_gmu_rpmh_init()
641 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); in a6xx_gmu_rpmh_init()
645 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
646 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); in a6xx_gmu_rpmh_init()
647 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); in a6xx_gmu_rpmh_init()
648 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()
650 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); in a6xx_gmu_rpmh_init()
651 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()
652 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); in a6xx_gmu_rpmh_init()
654 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); in a6xx_gmu_rpmh_init()
656 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); in a6xx_gmu_rpmh_init()
659 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
660 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); in a6xx_gmu_rpmh_init()
661 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); in a6xx_gmu_rpmh_init()
662 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()
665 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); in a6xx_gmu_rpmh_init()
666 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()
669 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); in a6xx_gmu_rpmh_init()
671 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); in a6xx_gmu_rpmh_init()
672 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); in a6xx_gmu_rpmh_init()
674 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); in a6xx_gmu_rpmh_init()
678 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); in a6xx_gmu_rpmh_init()
679 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); in a6xx_gmu_rpmh_init()
695 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
696 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
699 #define GMU_PWR_COL_HYST 0x000a1680
708 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); in a6xx_gmu_power_config()
709 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); in a6xx_gmu_power_config()
710 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); in a6xx_gmu_power_config()
716 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); in a6xx_gmu_power_config()
722 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
729 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
735 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, in a6xx_gmu_power_config()
770 u32 itcm_base = 0x00000000; in a6xx_gmu_fw_load()
771 u32 dtcm_base = 0x00040000; in a6xx_gmu_fw_load()
774 dtcm_base = 0x10004000; in a6xx_gmu_fw_load()
778 if (fw_image->size > 0x8000) { in a6xx_gmu_fw_load()
786 return 0; in a6xx_gmu_fw_load()
793 if (blk->size == 0) in a6xx_gmu_fw_load()
810 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", in a6xx_gmu_fw_load()
811 blk->addr, blk->size, blk->data[0]); in a6xx_gmu_fw_load()
821 return 0; in a6xx_gmu_fw_load()
830 u32 chipid = 0; in a6xx_gmu_fw_start()
864 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); in a6xx_gmu_fw_start()
865 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); in a6xx_gmu_fw_start()
872 fence_range_upper = 0x32; in a6xx_gmu_fw_start()
873 fence_range_lower = 0x8a0; in a6xx_gmu_fw_start()
875 fence_range_upper = 0xa; in a6xx_gmu_fw_start()
876 fence_range_lower = 0xa0; in a6xx_gmu_fw_start()
882 FIELD_PREP(GENMASK(17, 0), fence_range_lower)); in a6xx_gmu_fw_start()
888 gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); in a6xx_gmu_fw_start()
900 chipid = adreno_gpu->chip_id & 0xffff0000; in a6xx_gmu_fw_start()
901 chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ in a6xx_gmu_fw_start()
902 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ in a6xx_gmu_fw_start()
909 ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); in a6xx_gmu_fw_start()
944 return 0; in a6xx_gmu_fw_start()
960 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); in a6xx_gmu_irq_disable()
961 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); in a6xx_gmu_irq_disable()
968 u32 val, seqmem_off = 0; in a6xx_gmu_rpmh_off()
996 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); in a6xx_gmu_force_off()
1013 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7); in a6xx_gmu_force_off()
1014 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_gmu_force_off()
1037 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ in a6xx_gmu_set_initial_freq()
1070 0 /* Hardcode ACD to be disabled for now */); in a6xx_gmu_resume()
1101 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); in a6xx_gmu_resume()
1132 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); in a6xx_gmu_resume()
1211 "Unable to slumber GMU: status = 0%x/0%x\n", in a6xx_gmu_shutdown()
1239 return 0; in a6xx_gmu_stop()
1265 return 0; in a6xx_gmu_stop()
1293 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ in a6xx_gmu_memory_alloc()
1294 range_end = 0x80000000; in a6xx_gmu_memory_alloc()
1319 return 0; in a6xx_gmu_memory_alloc()
1326 mmu = msm_iommu_new(gmu->dev, 0); in a6xx_gmu_memory_probe()
1332 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); in a6xx_gmu_memory_probe()
1336 return 0; in a6xx_gmu_memory_probe()
1357 const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 }; in a6xx_gmu_rpmh_bw_votes_init()
1358 unsigned int bcm_index, bw_index, bcm_count = 0; in a6xx_gmu_rpmh_bw_votes_init()
1361 for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { in a6xx_gmu_rpmh_bw_votes_init()
1383 for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) { in a6xx_gmu_rpmh_bw_votes_init()
1388 for (bcm_index = 0; bcm_index < bcm_count; bcm_index++) { in a6xx_gmu_rpmh_bw_votes_init()
1400 data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0); in a6xx_gmu_rpmh_bw_votes_init()
1405 u32 perfmode = 0; in a6xx_gmu_rpmh_bw_votes_init()
1412 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode); in a6xx_gmu_rpmh_bw_votes_init()
1430 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote); in a6xx_gmu_rpmh_bw_votes_init()
1434 return 0; in a6xx_gmu_rpmh_bw_votes_init()
1445 return 0; in a6xx_gmu_get_arc_level()
1449 return 0; in a6xx_gmu_get_arc_level()
1491 for (i = 0; i < freqs_count; i++) { in a6xx_gmu_rpmh_arc_votes_init()
1492 u8 pindex = 0, sindex = 0; in a6xx_gmu_rpmh_arc_votes_init()
1496 for (j = 0; j < pri_count; j++) { in a6xx_gmu_rpmh_arc_votes_init()
1508 for (j = 0; j < pri_count; j++) in a6xx_gmu_rpmh_arc_votes_init()
1519 for (j = 0; j < sec_count; j++) { in a6xx_gmu_rpmh_arc_votes_init()
1529 votes[i] = ((pri[pindex] & 0xffff) << 16) | in a6xx_gmu_rpmh_arc_votes_init()
1533 return 0; in a6xx_gmu_rpmh_arc_votes_init()
1572 int i, index = 0; in a6xx_gmu_build_freq_table()
1585 freqs[index++] = 0; in a6xx_gmu_build_freq_table()
1587 for (i = 0; i < count; i++) { in a6xx_gmu_build_freq_table()
1604 int i, index = 0; in a6xx_gmu_build_bw_table()
1617 bandwidths[index++] = 0; in a6xx_gmu_build_bw_table()
1619 for (i = 0; i < count; i++) { in a6xx_gmu_build_bw_table()
1620 opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0); in a6xx_gmu_build_bw_table()
1638 int ret = 0; in a6xx_gmu_pwrlevels_probe()
1689 return 0; in a6xx_gmu_clocks_probe()
1787 return 0; in cxpd_notifier_cb()
1841 return 0; in a6xx_gmu_wrapper_init()
1897 0x60400000, "debug"); in a6xx_gmu_init()
1906 0x60000000, "dummy"); in a6xx_gmu_init()
1914 SZ_16M - SZ_16K, 0x04000, "icache"); in a6xx_gmu_init()
1925 SZ_256K - SZ_16K, 0x04000, "icache"); in a6xx_gmu_init()
1930 SZ_256K - SZ_16K, 0x44000, "dcache"); in a6xx_gmu_init()
1938 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug"); in a6xx_gmu_init()
1944 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log"); in a6xx_gmu_init()
1949 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); in a6xx_gmu_init()
1968 gmu->rscc = gmu->mmio + 0x23000; in a6xx_gmu_init()
1975 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) { in a6xx_gmu_init()
2019 return 0; in a6xx_gmu_init()