Lines Matching +full:0 +full:x03900000
94 #define HDMITX_TOP_ADDR_REG 0x0
95 #define HDMITX_TOP_DATA_REG 0x4
96 #define HDMITX_TOP_CTRL_REG 0x8
97 #define HDMITX_TOP_G12A_OFFSET 0x8000
100 #define HDMITX_DWC_ADDR_REG 0x10
101 #define HDMITX_DWC_DATA_REG 0x14
102 #define HDMITX_DWC_CTRL_REG 0x18
105 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
106 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
107 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
108 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
109 #define PHY_CNTL1_INIT 0x03900000
111 #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
112 #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
113 #define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
114 #define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
119 MESON_VENC_SOURCE_NONE = 0,
170 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
171 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
196 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
197 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
234 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
235 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
260 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
261 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
292 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282); in meson_hdmi_phy_setup_mode()
293 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); in meson_hdmi_phy_setup_mode()
296 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); in meson_hdmi_phy_setup_mode()
297 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); in meson_hdmi_phy_setup_mode()
300 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362); in meson_hdmi_phy_setup_mode()
301 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b); in meson_hdmi_phy_setup_mode()
304 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142); in meson_hdmi_phy_setup_mode()
305 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b); in meson_hdmi_phy_setup_mode()
311 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245); in meson_hdmi_phy_setup_mode()
312 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b); in meson_hdmi_phy_setup_mode()
315 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283); in meson_hdmi_phy_setup_mode()
316 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b); in meson_hdmi_phy_setup_mode()
319 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122); in meson_hdmi_phy_setup_mode()
320 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b); in meson_hdmi_phy_setup_mode()
326 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4); in meson_hdmi_phy_setup_mode()
327 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
328 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b); in meson_hdmi_phy_setup_mode()
331 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262); in meson_hdmi_phy_setup_mode()
332 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
333 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); in meson_hdmi_phy_setup_mode()
336 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242); in meson_hdmi_phy_setup_mode()
337 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
338 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); in meson_hdmi_phy_setup_mode()
348 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); in meson_dw_hdmi_phy_reset()
353 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); in meson_dw_hdmi_phy_reset()
380 0); in dw_hdmi_phy_init()
382 0x03ff03ff); in dw_hdmi_phy_init()
385 0x001f001f); in dw_hdmi_phy_init()
387 0x001f001f); in dw_hdmi_phy_init()
391 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); in dw_hdmi_phy_init()
393 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); in dw_hdmi_phy_init()
399 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); in dw_hdmi_phy_init()
412 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
414 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
417 writel_bits_relaxed(0x3, 0, in dw_hdmi_phy_init()
419 writel_bits_relaxed(0xf << 8, 0, in dw_hdmi_phy_init()
429 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), in dw_hdmi_phy_init()
434 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, in dw_hdmi_phy_init()
437 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, in dw_hdmi_phy_init()
440 return 0; in dw_hdmi_phy_init()
472 (0xa << 12) | 0xa0); in dw_hdmi_setup_hpd()
548 return 0; in meson_dw_hdmi_reg_read()
559 return 0; in meson_dw_hdmi_reg_write()
567 .max_register = 0x10000,
576 .cntl0_init = 0x0,
585 .cntl0_init = 0x0,
594 .cntl0_init = 0x000b4242, /* Bandgap */
603 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
606 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); in meson_dw_hdmi_init()
623 HDMITX_TOP_SW_RESET, 0); in meson_dw_hdmi_init()
628 HDMITX_TOP_CLK_CNTL, 0xff); in meson_dw_hdmi_init()
700 if (ret < 0 && ret != -ENODEV) in meson_dw_hdmi_bind()
724 meson_dw_hdmi->hdmitx = devm_platform_ioremap_resource(pdev, 0); in meson_dw_hdmi_bind()
745 irq = platform_get_irq(pdev, 0); in meson_dw_hdmi_bind()
746 if (irq < 0) in meson_dw_hdmi_bind()
785 return 0; in meson_dw_hdmi_bind()
806 return 0; in meson_dw_hdmi_pm_suspend()
810 HDMITX_TOP_SW_RESET, 0); in meson_dw_hdmi_pm_suspend()
812 return 0; in meson_dw_hdmi_pm_suspend()
820 return 0; in meson_dw_hdmi_pm_resume()
826 return 0; in meson_dw_hdmi_pm_resume()