1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/soc/mediatek/mtk-cmdq.h>
16 #include <linux/soc/mediatek/mtk-mmsys.h>
108 	priv->vblank_cb = vblank_cb;  in mtk_ethdr_register_vblank_cb()
109 	priv->vblank_cb_data = vblank_cb_data;  in mtk_ethdr_register_vblank_cb()
116 	priv->vblank_cb = NULL;  in mtk_ethdr_unregister_vblank_cb()
117 	priv->vblank_cb_data = NULL;  in mtk_ethdr_unregister_vblank_cb()
124 	writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);  in mtk_ethdr_enable_vblank()
131 	writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);  in mtk_ethdr_disable_vblank()
138 	writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);  in mtk_ethdr_irq_handler()
140 	if (!priv->vblank_cb)  in mtk_ethdr_irq_handler()
143 	priv->vblank_cb(priv->vblank_cb_data);  in mtk_ethdr_irq_handler()
160 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];  in mtk_ethdr_layer_config()
161 	struct mtk_plane_pending_state *pending = &state->pending;  in mtk_ethdr_layer_config()
162 	unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;  in mtk_ethdr_layer_config()
163 	unsigned int align_width = ALIGN_DOWN(pending->width, 2);  in mtk_ethdr_layer_config()
172 	if (!pending->enable || !pending->width || !pending->height) {  in mtk_ethdr_layer_config()
178 		mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));  in mtk_ethdr_layer_config()
182 	if (state->base.fb) {  in mtk_ethdr_layer_config()
184 		alpha_con |= state->base.alpha & MIXER_ALPHA;  in mtk_ethdr_layer_config()
187 	if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)  in mtk_ethdr_layer_config()
192 	if ((state->base.fb && !state->base.fb->format->has_alpha) ||  in mtk_ethdr_layer_config()
193 	    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {  in mtk_ethdr_layer_config()
201 	mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a,  in mtk_ethdr_layer_config()
203 				  pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :  in mtk_ethdr_layer_config()
204 				  MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);  in mtk_ethdr_layer_config()
206 	mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,  in mtk_ethdr_layer_config()
207 		      mixer->regs, MIX_L_SRC_SIZE(idx));  in mtk_ethdr_layer_config()
208 	mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));  in mtk_ethdr_layer_config()
209 	mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));  in mtk_ethdr_layer_config()
210 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,  in mtk_ethdr_layer_config()
219 	struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];  in mtk_ethdr_config()
220 	struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];  in mtk_ethdr_config()
221 	struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];  in mtk_ethdr_config()
222 	struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];  in mtk_ethdr_config()
223 	struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];  in mtk_ethdr_config()
224 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];  in mtk_ethdr_config()
226 	dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);  in mtk_ethdr_config()
228 	mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,  in mtk_ethdr_config()
229 		      vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);  in mtk_ethdr_config()
231 	mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,  in mtk_ethdr_config()
232 		      vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);  in mtk_ethdr_config()
234 	mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,  in mtk_ethdr_config()
235 		      gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);  in mtk_ethdr_config()
237 	mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,  in mtk_ethdr_config()
238 		      gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);  in mtk_ethdr_config()
240 	mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,  in mtk_ethdr_config()
241 		      vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);  in mtk_ethdr_config()
243 	mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);  in mtk_ethdr_config()
244 	mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);  in mtk_ethdr_config()
245 	mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);  in mtk_ethdr_config()
246 	mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);  in mtk_ethdr_config()
247 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,  in mtk_ethdr_config()
249 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,  in mtk_ethdr_config()
251 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,  in mtk_ethdr_config()
253 	mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,  in mtk_ethdr_config()
255 	mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));  in mtk_ethdr_config()
257 		      &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);  in mtk_ethdr_config()
258 	mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,  in mtk_ethdr_config()
261 	mtk_mmsys_hdr_config(priv->mmsys_dev, w / 2, h, cmdq_pkt);  in mtk_ethdr_config()
262 	mtk_mmsys_mixer_in_channel_swap(priv->mmsys_dev, 4, 0, cmdq_pkt);  in mtk_ethdr_config()
268 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];  in mtk_ethdr_start()
270 	writel(1, mixer->regs + MIX_EN);  in mtk_ethdr_start()
276 	struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];  in mtk_ethdr_stop()
278 	writel(0, mixer->regs + MIX_EN);  in mtk_ethdr_stop()
279 	writel(1, mixer->regs + MIX_RST);  in mtk_ethdr_stop()
280 	reset_control_reset(priv->reset_ctl);  in mtk_ethdr_stop()
281 	writel(0, mixer->regs + MIX_RST);  in mtk_ethdr_stop()
289 	ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);  in mtk_ethdr_clk_enable()
300 	clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);  in mtk_ethdr_clk_disable()
308 	priv->mmsys_dev = data;  in mtk_ethdr_bind()
323 	struct device *dev = &pdev->dev;  in mtk_ethdr_probe()
330 		return -ENOMEM;  in mtk_ethdr_probe()
333 		priv->ethdr_comp[i].dev = dev;  in mtk_ethdr_probe()
334 		priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);  in mtk_ethdr_probe()
337 					      &priv->ethdr_comp[i].cmdq_base, i);  in mtk_ethdr_probe()
339 			dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");  in mtk_ethdr_probe()
341 		dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i);  in mtk_ethdr_probe()
345 		priv->ethdr_clk[i].id = ethdr_clk_str[i];  in mtk_ethdr_probe()
346 	ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);  in mtk_ethdr_probe()
350 	priv->irq = platform_get_irq(pdev, 0);  in mtk_ethdr_probe()
351 	if (priv->irq < 0)  in mtk_ethdr_probe()
352 		priv->irq = 0;  in mtk_ethdr_probe()
354 	if (priv->irq) {  in mtk_ethdr_probe()
355 		ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,  in mtk_ethdr_probe()
360 					     priv->irq);  in mtk_ethdr_probe()
363 	priv->reset_ctl = devm_reset_control_array_get_optional_exclusive(dev);  in mtk_ethdr_probe()
364 	if (IS_ERR(priv->reset_ctl))  in mtk_ethdr_probe()
365 		return dev_err_probe(dev, PTR_ERR(priv->reset_ctl),  in mtk_ethdr_probe()
366 				     "cannot get ethdr reset control\n");  in mtk_ethdr_probe()
379 	component_del(&pdev->dev, &mtk_ethdr_component_ops);  in mtk_ethdr_remove()
383 	{ .compatible = "mediatek,mt8195-disp-ethdr"},
393 		.name	= "mediatek-disp-ethdr",