Lines Matching +full:8 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
28 #define DA_CKM_XTAL_CK_FORCE_EN BIT(8)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
65 #define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8)
66 #define DP_TX1_VOLT_SWING_SHIFT 8
87 #define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8)
91 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
93 #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
95 #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
97 #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
99 #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
101 #define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
104 #define HSP_SW_DP_ENC0_P0_MASK BIT(15)
107 #define VSP_SW_DP_ENC0_P0_MASK BIT(15)
117 #define VSP_SEL_DP_ENC0_P0 BIT(8)
126 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8)
127 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8)
128 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << 8)
129 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT (2 << 8)
130 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << 8)
131 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << 8)
136 #define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15)
142 #define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK BIT(8)
144 #define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)
148 #define AUDIO_8CH_SEL_DP_ENC0_P0_MASK BIT(8)
150 #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15)
152 #define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)
154 #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
162 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)
163 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
164 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)
165 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8)
166 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8)
167 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8)
168 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)
169 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
170 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)
171 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8)
172 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8)
173 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << 8)
174 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)
178 #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
204 #define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
214 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)
216 #define AU_PRTY_REGEN_DP_ENC1_P0_MASK BIT(8)
220 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK GENMASK(9, 8)
226 #define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12)
230 #define SDP_DP13_EN_DP_ENC1_P0 BIT(8)
252 #define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15)
262 #define HPD_DISC_THD_DP_TRANS_P0_MASK GENMASK(11, 8)
263 #define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12)
272 #define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12)
285 #define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK BIT(8)
290 #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)
291 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
293 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
310 #define AUX_RX_FIFO_READ_PULSE_TX_P0 BIT(8)
320 #define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2)
324 #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)
344 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
348 #define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)
350 #define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 BIT(8)
354 #define RX_REPLY_COMPLETE_MODE_AUX_TX_P0 BIT(8)