Lines Matching full:15
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
91 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
93 #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
95 #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
97 #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
99 #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
101 #define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
104 #define HSP_SW_DP_ENC0_P0_MASK BIT(15)
107 #define VSP_SW_DP_ENC0_P0_MASK BIT(15)
136 #define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15)
144 #define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)
150 #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15)
152 #define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)
154 #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
178 #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
204 #define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
226 #define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12)
252 #define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15)
263 #define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12)
272 #define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12)
290 #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)
291 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
293 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
320 #define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2)
324 #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)
344 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
348 #define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)