Lines Matching +full:9 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
14 #define LCD_CTRL_INTERLACED BIT(0)
15 #define LCD_CTRL_ENABLE BIT(1)
16 #define LCD_CTRL_VL1_ENABLE BIT(2)
17 #define LCD_CTRL_VL2_ENABLE BIT(3)
18 #define LCD_CTRL_GL1_ENABLE BIT(4)
19 #define LCD_CTRL_GL2_ENABLE BIT(5)
21 #define LCD_CTRL_ALPHA_BLEND_VL2 BIT(6)
25 #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8)
29 #define LCD_CTRL_ALPHA_MIDDLE_VL2 BIT(10)
33 #define LCD_CTRL_ALPHA_BOTTOM_VL2 BIT(12)
36 #define LCD_CTRL_TIM_GEN_ENABLE BIT(14)
38 #define LCD_CTRL_ONE_SHOT BIT(15)
39 #define LCD_CTRL_PWM0_EN BIT(16)
40 #define LCD_CTRL_PWM1_EN BIT(17)
41 #define LCD_CTRL_PWM2_EN BIT(18)
43 #define LCD_CTRL_OUTPUT_ENABLED BIT(19)
44 #define LCD_CTRL_BPORCH_ENABLE BIT(21)
45 #define LCD_CTRL_FPORCH_ENABLE BIT(22)
46 #define LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE BIT(23)
47 #define LCD_CTRL_PIPELINE_DMA BIT(28)
48 #define LCD_CTRL_VHSYNC_IDLE_LVL BIT(31)
53 #define LCD_INT_EOF BIT(0)
54 #define LCD_INT_LINE_CMP BIT(1)
55 #define LCD_INT_VERT_COMP BIT(2)
56 #define LAYER0_DMA_DONE BIT(3)
57 #define LAYER0_DMA_IDLE BIT(4)
58 #define LAYER0_DMA_FIFO_OVERFLOW BIT(5)
59 #define LAYER0_DMA_FIFO_UNDERFLOW BIT(6)
60 #define LAYER0_DMA_CB_FIFO_OVERFLOW BIT(7)
61 #define LAYER0_DMA_CB_FIFO_UNDERFLOW BIT(8)
62 #define LAYER0_DMA_CR_FIFO_OVERFLOW BIT(9)
63 #define LAYER0_DMA_CR_FIFO_UNDERFLOW BIT(10)
64 #define LAYER1_DMA_DONE BIT(11)
65 #define LAYER1_DMA_IDLE BIT(12)
66 #define LAYER1_DMA_FIFO_OVERFLOW BIT(13)
67 #define LAYER1_DMA_FIFO_UNDERFLOW BIT(14)
68 #define LAYER1_DMA_CB_FIFO_OVERFLOW BIT(15)
69 #define LAYER1_DMA_CB_FIFO_UNDERFLOW BIT(16)
70 #define LAYER1_DMA_CR_FIFO_OVERFLOW BIT(17)
71 #define LAYER1_DMA_CR_FIFO_UNDERFLOW BIT(18)
72 #define LAYER2_DMA_DONE BIT(19)
73 #define LAYER2_DMA_IDLE BIT(20)
74 #define LAYER2_DMA_FIFO_OVERFLOW BIT(21)
75 #define LAYER2_DMA_FIFO_UNDERFLOW BIT(22)
76 #define LAYER3_DMA_DONE BIT(23)
77 #define LAYER3_DMA_IDLE BIT(24)
78 #define LAYER3_DMA_FIFO_OVERFLOW BIT(25)
79 #define LAYER3_DMA_FIFO_UNDERFLOW BIT(26)
94 #define LCD_VSTATUS_COMPARE_BACKPORCH BIT(13)
111 #define LCD_LAYER_SCALE_H BIT(1)
112 #define LCD_LAYER_SCALE_V BIT(2)
115 #define LCD_LAYER_CSC_EN BIT(3)
116 #define LCD_LAYER_ALPHA_STATIC BIT(4)
117 #define LCD_LAYER_ALPHA_EMBED BIT(5)
122 #define LCD_LAYER_ALPHA_PREMULT BIT(6)
123 #define LCD_LAYER_INVERT_COL BIT(7)
124 #define LCD_LAYER_TRANSPARENT_EN BIT(8)
125 #define LCD_LAYER_FORMAT_YCBCR444PLAN (0 << 9)
126 #define LCD_LAYER_FORMAT_YCBCR422PLAN BIT(9)
127 #define LCD_LAYER_FORMAT_YCBCR420PLAN (2 << 9)
128 #define LCD_LAYER_FORMAT_RGB888PLAN (3 << 9)
129 #define LCD_LAYER_FORMAT_YCBCR444LIN (4 << 9)
130 #define LCD_LAYER_FORMAT_YCBCR422LIN (5 << 9)
131 #define LCD_LAYER_FORMAT_RGB888 (6 << 9)
132 #define LCD_LAYER_FORMAT_RGBA8888 (7 << 9)
133 #define LCD_LAYER_FORMAT_RGBX8888 (8 << 9)
134 #define LCD_LAYER_FORMAT_RGB565 (9 << 9)
135 #define LCD_LAYER_FORMAT_RGBA1555 (0xa << 9)
136 #define LCD_LAYER_FORMAT_XRGB1555 (0xb << 9)
137 #define LCD_LAYER_FORMAT_RGB444 (0xc << 9)
138 #define LCD_LAYER_FORMAT_RGBA4444 (0xd << 9)
139 #define LCD_LAYER_FORMAT_RGBX4444 (0xe << 9)
140 #define LCD_LAYER_FORMAT_RGB332 (0xf << 9)
141 #define LCD_LAYER_FORMAT_RGBA3328 (0x10 << 9)
142 #define LCD_LAYER_FORMAT_RGBX3328 (0x11 << 9)
143 #define LCD_LAYER_FORMAT_CLUT (0x12 << 9)
144 #define LCD_LAYER_FORMAT_NV12 (0x1c << 9)
145 #define LCD_LAYER_PLANAR_STORAGE BIT(14)
147 #define LCD_LAYER_16BPP BIT(15)
150 #define LCD_LAYER_Y_ORDER BIT(17)
151 #define LCD_LAYER_CRCB_ORDER BIT(18)
152 #define LCD_LAYER_BGR_ORDER BIT(19)
154 #define LCD_LAYER_LUT_4ENT BIT(20)
157 #define LCD_LAYER_FLIP_V BIT(22)
163 #define LCD_LAYER_FIFO_25 BIT(25)
167 #define LCD_LAYER_INTERLEAVE_V BIT(27)
174 #define LCD_LAYER_INTER_POS_ODD BIT(30)
229 #define LCD_DMA_LAYER_ENABLE BIT(0)
230 #define LCD_DMA_LAYER_STATUS BIT(1)
231 #define LCD_DMA_LAYER_AUTO_UPDATE BIT(2)
232 #define LCD_DMA_LAYER_CONT_UPDATE BIT(3)
235 #define LCD_DMA_LAYER_FIFO_ADR_MODE BIT(4)
236 #define LCD_DMA_LAYER_AXI_BURST_1 BIT(5)
244 #define LCD_DMA_LAYER_AXI_BURST_9 (9 << 5)
252 #define LCD_DMA_LAYER_VSTRIDE_EN BIT(10)
345 #define LCD_OUTF_BGR_ORDER BIT(5)
346 #define LCD_OUTF_Y_ORDER BIT(6)
347 #define LCD_OUTF_CRCB_ORDER BIT(7)
348 #define LCD_OUTF_SYNC_MODE BIT(11)
349 #define LCD_OUTF_RGB_CONV_MODE BIT(14)
350 #define LCD_OUTF_MIPI_RGB_MODE BIT(18)
380 #define LCD_DMA_STATE_ACTIVE BIT(3)
404 #define HS_CTRL_EN BIT(0)
406 #define HS_CTRL_CSIDSIN BIT(2)
408 #define TX_SOURCE BIT(3)
411 #define DSI_EOTP_EN BIT(11)
412 #define DSI_CMD_HFP_EN BIT(12)
413 #define CRC_EN BIT(14)
415 #define HSCLKIDLE_CNT BIT(24)
419 #define LINE_SYNC_PKT_ENABLE BIT(0)
420 #define FRAME_COUNTER_ACTIVE BIT(1)
421 #define LINE_COUNTER_ACTIVE BIT(2)
422 #define DSI_V_BLANKING BIT(4)
423 #define DSI_HSA_BLANKING BIT(5)
424 #define DSI_HBP_BLANKING BIT(6)
425 #define DSI_HFP_BLANKING BIT(7)
426 #define DSI_SYNC_PULSE_EVENTN BIT(8)
427 #define DSI_LPM_FIRST_VSA_LINE BIT(9)
428 #define DSI_LPM_LAST_VFP_LINE BIT(10)
429 #define WAIT_ALL_SECT BIT(11)
430 #define WAIT_TRIG_POS BIT(15)
445 #define MIPI_TX_SECT_DMA_PACKED BIT(26)
533 #define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */
535 /* bits 13-22 */
565 #define MIPI_TX_HS_IRQ_LINE_COMPARE BIT(1)
566 #define MIPI_TX_HS_IRQ_FRAME_DONE_0 BIT(2)
567 #define MIPI_TX_HS_IRQ_FRAME_DONE_1 BIT(3)
568 #define MIPI_TX_HS_IRQ_FRAME_DONE_2 BIT(4)
569 #define MIPI_TX_HS_IRQ_FRAME_DONE_3 BIT(5)
570 #define MIPI_TX_HS_IRQ_DMA_DONE_0 BIT(6)
571 #define MIPI_TX_HS_IRQ_DMA_IDLE_0 BIT(7)
572 #define MIPI_TX_HS_IRQ_DMA_DONE_1 BIT(8)
573 #define MIPI_TX_HS_IRQ_DMA_IDLE_1 BIT(9)
574 #define MIPI_TX_HS_IRQ_DMA_DONE_2 BIT(10)
575 #define MIPI_TX_HS_IRQ_DMA_IDLE_2 BIT(11)
576 #define MIPI_TX_HS_IRQ_DMA_DONE_3 BIT(12)
577 #define MIPI_TX_HS_IRQ_DMA_IDLE_3 BIT(13)
578 #define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW BIT(14)
579 #define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW BIT(15)
580 #define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY BIT(16)
581 #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL BIT(17)
582 #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR BIT(18)
583 #define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR BIT(20)
638 /* D-PHY regs */
707 & (1 << ((dphy) - MIPI_DPHY6)))
714 #define LCD BIT(1)
715 #define MIPI_COMMON BIT(2)
716 #define MIPI_TX0 BIT(9)