22 int intel_gmch_bridge_setup(struct drm_i915_private *i915)  in intel_gmch_bridge_setup()  argument
24 	int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);  in intel_gmch_bridge_setup()
26 	i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));  in intel_gmch_bridge_setup()
27 	if (!i915->gmch.pdev) {  in intel_gmch_bridge_setup()
28 		drm_err(&i915->drm, "bridge device not found\n");  in intel_gmch_bridge_setup()
32 	return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,  in intel_gmch_bridge_setup()
33 					i915->gmch.pdev);  in intel_gmch_bridge_setup()
36 static int mchbar_reg(struct drm_i915_private *i915)  in mchbar_reg()  argument
38 	return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;  in mchbar_reg()
43 intel_alloc_mchbar_resource(struct drm_i915_private *i915)  in intel_alloc_mchbar_resource()  argument
49 	if (GRAPHICS_VER(i915) >= 4)  in intel_alloc_mchbar_resource()
50 		pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi);  in intel_alloc_mchbar_resource()
51 	pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo);  in intel_alloc_mchbar_resource()
60 	i915->gmch.mch_res.name = "i915 MCHBAR";  in intel_alloc_mchbar_resource()
61 	i915->gmch.mch_res.flags = IORESOURCE_MEM;  in intel_alloc_mchbar_resource()
62 	ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,  in intel_alloc_mchbar_resource()
63 				     &i915->gmch.mch_res,  in intel_alloc_mchbar_resource()
67 				     i915->gmch.pdev);  in intel_alloc_mchbar_resource()
69 		drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);  in intel_alloc_mchbar_resource()
70 		i915->gmch.mch_res.start = 0;  in intel_alloc_mchbar_resource()
74 	if (GRAPHICS_VER(i915) >= 4)  in intel_alloc_mchbar_resource()
75 		pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4,  in intel_alloc_mchbar_resource()
76 				       upper_32_bits(i915->gmch.mch_res.start));  in intel_alloc_mchbar_resource()
78 	pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),  in intel_alloc_mchbar_resource()
79 			       lower_32_bits(i915->gmch.mch_res.start));  in intel_alloc_mchbar_resource()
84 void intel_gmch_bar_setup(struct drm_i915_private *i915)  in intel_gmch_bar_setup()  argument
89 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))  in intel_gmch_bar_setup()
92 	i915->gmch.mchbar_need_disable = false;  in intel_gmch_bar_setup()
94 	if (IS_I915G(i915) || IS_I915GM(i915)) {  in intel_gmch_bar_setup()
95 		pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);  in intel_gmch_bar_setup()
98 		pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);  in intel_gmch_bar_setup()
106 	if (intel_alloc_mchbar_resource(i915))  in intel_gmch_bar_setup()
109 	i915->gmch.mchbar_need_disable = true;  in intel_gmch_bar_setup()
112 	if (IS_I915G(i915) || IS_I915GM(i915)) {  in intel_gmch_bar_setup()
113 		pci_write_config_dword(i915->gmch.pdev, DEVEN,  in intel_gmch_bar_setup()
116 		pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);  in intel_gmch_bar_setup()
117 		pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1);  in intel_gmch_bar_setup()
121 void intel_gmch_bar_teardown(struct drm_i915_private *i915)  in intel_gmch_bar_teardown()  argument
123 	if (i915->gmch.mchbar_need_disable) {  in intel_gmch_bar_teardown()
124 		if (IS_I915G(i915) || IS_I915GM(i915)) {  in intel_gmch_bar_teardown()
127 			pci_read_config_dword(i915->gmch.pdev, DEVEN,  in intel_gmch_bar_teardown()
130 			pci_write_config_dword(i915->gmch.pdev, DEVEN,  in intel_gmch_bar_teardown()
135 			pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915),  in intel_gmch_bar_teardown()
138 			pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),  in intel_gmch_bar_teardown()
143 	if (i915->gmch.mch_res.start)  in intel_gmch_bar_teardown()
144 		release_resource(&i915->gmch.mch_res);  in intel_gmch_bar_teardown()
147 int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)  in intel_gmch_vga_set_state()  argument
149 	unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;  in intel_gmch_vga_set_state()
152 	if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {  in intel_gmch_vga_set_state()
153 		drm_err(&i915->drm, "failed to read control word\n");  in intel_gmch_vga_set_state()
165 	if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {  in intel_gmch_vga_set_state()
166 		drm_err(&i915->drm, "failed to write control word\n");  in intel_gmch_vga_set_state()
175 	struct drm_i915_private *i915 = pdev_to_i915(pdev);  in intel_gmch_vga_set_decode()  local
177 	intel_gmch_vga_set_state(i915, enable_decode);  in intel_gmch_vga_set_decode()