46 static bool pnv_is_ddr3(struct drm_i915_private *i915)  in pnv_is_ddr3()  argument
48 	return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;  in pnv_is_ddr3()
90 static unsigned int chv_mem_freq(struct drm_i915_private *i915)  in chv_mem_freq()  argument
94 	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));  in chv_mem_freq()
95 	val = vlv_cck_read(i915, CCK_FUSE_REG);  in chv_mem_freq()
96 	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));  in chv_mem_freq()
106 static unsigned int vlv_mem_freq(struct drm_i915_private *i915)  in vlv_mem_freq()  argument
110 	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));  in vlv_mem_freq()
111 	val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);  in vlv_mem_freq()
112 	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));  in vlv_mem_freq()
127 static void detect_mem_freq(struct drm_i915_private *i915)  in detect_mem_freq()  argument
129 	if (IS_PINEVIEW(i915))  in detect_mem_freq()
130 		i915->mem_freq = pnv_mem_freq(i915);  in detect_mem_freq()
131 	else if (GRAPHICS_VER(i915) == 5)  in detect_mem_freq()
132 		i915->mem_freq = ilk_mem_freq(i915);  in detect_mem_freq()
133 	else if (IS_CHERRYVIEW(i915))  in detect_mem_freq()
134 		i915->mem_freq = chv_mem_freq(i915);  in detect_mem_freq()
135 	else if (IS_VALLEYVIEW(i915))  in detect_mem_freq()
136 		i915->mem_freq = vlv_mem_freq(i915);  in detect_mem_freq()
138 	if (IS_PINEVIEW(i915))  in detect_mem_freq()
139 		i915->is_ddr3 = pnv_is_ddr3(i915);  in detect_mem_freq()
141 	if (i915->mem_freq)  in detect_mem_freq()
142 		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);  in detect_mem_freq()
145 unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)  in i9xx_fsb_freq()  argument
157 	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;  in i9xx_fsb_freq()
159 	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {  in i9xx_fsb_freq()
227 static void detect_fsb_freq(struct drm_i915_private *i915)  in detect_fsb_freq()  argument
229 	if (GRAPHICS_VER(i915) == 5)  in detect_fsb_freq()
230 		i915->fsb_freq = ilk_fsb_freq(i915);  in detect_fsb_freq()
231 	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)  in detect_fsb_freq()
232 		i915->fsb_freq = i9xx_fsb_freq(i915);  in detect_fsb_freq()
234 	if (i915->fsb_freq)  in detect_fsb_freq()
235 		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);  in detect_fsb_freq()
317 skl_dram_get_dimm_info(struct drm_i915_private *i915,  in skl_dram_get_dimm_info()  argument
321 	if (GRAPHICS_VER(i915) >= 11) {  in skl_dram_get_dimm_info()
331 	drm_dbg_kms(&i915->drm,  in skl_dram_get_dimm_info()
338 skl_dram_get_channel_info(struct drm_i915_private *i915,  in skl_dram_get_channel_info()  argument
342 	skl_dram_get_dimm_info(i915, &ch->dimm_l,  in skl_dram_get_channel_info()
344 	skl_dram_get_dimm_info(i915, &ch->dimm_s,  in skl_dram_get_channel_info()
348 		drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);  in skl_dram_get_channel_info()
362 	drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",  in skl_dram_get_channel_info()
378 skl_dram_get_channels_info(struct drm_i915_private *i915)  in skl_dram_get_channels_info()  argument
380 	struct dram_info *dram_info = &i915->dram_info;  in skl_dram_get_channels_info()
385 	val = intel_uncore_read(&i915->uncore,  in skl_dram_get_channels_info()
387 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);  in skl_dram_get_channels_info()
391 	val = intel_uncore_read(&i915->uncore,  in skl_dram_get_channels_info()
393 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);  in skl_dram_get_channels_info()
398 		drm_info(&i915->drm, "Number of memory channels is zero\n");  in skl_dram_get_channels_info()
403 		drm_info(&i915->drm, "couldn't get memory rank information\n");  in skl_dram_get_channels_info()
411 	drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",  in skl_dram_get_channels_info()
418 skl_get_dram_type(struct drm_i915_private *i915)  in skl_get_dram_type()  argument
422 	val = intel_uncore_read(&i915->uncore,  in skl_get_dram_type()
441 skl_get_dram_info(struct drm_i915_private *i915)  in skl_get_dram_info()  argument
443 	struct dram_info *dram_info = &i915->dram_info;  in skl_get_dram_info()
446 	dram_info->type = skl_get_dram_type(i915);  in skl_get_dram_info()
447 	drm_dbg_kms(&i915->drm, "DRAM type: %s\n",  in skl_get_dram_info()
450 	ret = skl_dram_get_channels_info(i915);  in skl_get_dram_info()
535 static int bxt_get_dram_info(struct drm_i915_private *i915)  in bxt_get_dram_info()  argument
537 	struct dram_info *dram_info = &i915->dram_info;  in bxt_get_dram_info()
549 		val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));  in bxt_get_dram_info()
558 		drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&  in bxt_get_dram_info()
562 		drm_dbg_kms(&i915->drm,  in bxt_get_dram_info()
576 		drm_info(&i915->drm, "couldn't get memory information\n");  in bxt_get_dram_info()
645 static int gen11_get_dram_info(struct drm_i915_private *i915)  in gen11_get_dram_info()  argument
647 	int ret = skl_get_dram_info(i915);  in gen11_get_dram_info()
652 	return icl_pcode_read_mem_global_info(i915);  in gen11_get_dram_info()
655 static int gen12_get_dram_info(struct drm_i915_private *i915)  in gen12_get_dram_info()  argument
657 	i915->dram_info.wm_lv_0_adjust_needed = false;  in gen12_get_dram_info()
659 	return icl_pcode_read_mem_global_info(i915);  in gen12_get_dram_info()
662 static int xelpdp_get_dram_info(struct drm_i915_private *i915)  in xelpdp_get_dram_info()  argument
664 	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);  in xelpdp_get_dram_info()
665 	struct dram_info *dram_info = &i915->dram_info;  in xelpdp_get_dram_info()
687 		drm_WARN_ON(&i915->drm, !IS_DGFX(i915));  in xelpdp_get_dram_info()
691 		drm_WARN_ON(&i915->drm, !IS_DGFX(i915));  in xelpdp_get_dram_info()
706 void intel_dram_detect(struct drm_i915_private *i915)  in intel_dram_detect()  argument
708 	struct dram_info *dram_info = &i915->dram_info;  in intel_dram_detect()
711 	detect_fsb_freq(i915);  in intel_dram_detect()
712 	detect_mem_freq(i915);  in intel_dram_detect()
714 	if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))  in intel_dram_detect()
721 	dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);  in intel_dram_detect()
723 	if (DISPLAY_VER(i915) >= 14)  in intel_dram_detect()
724 		ret = xelpdp_get_dram_info(i915);  in intel_dram_detect()
725 	else if (GRAPHICS_VER(i915) >= 12)  in intel_dram_detect()
726 		ret = gen12_get_dram_info(i915);  in intel_dram_detect()
727 	else if (GRAPHICS_VER(i915) >= 11)  in intel_dram_detect()
728 		ret = gen11_get_dram_info(i915);  in intel_dram_detect()
729 	else if (IS_BROXTON(i915) || IS_GEMINILAKE(i915))  in intel_dram_detect()
730 		ret = bxt_get_dram_info(i915);  in intel_dram_detect()
732 		ret = skl_get_dram_info(i915);  in intel_dram_detect()
736 	drm_dbg_kms(&i915->drm, "Num qgv points %u\n", dram_info->num_qgv_points);  in intel_dram_detect()
738 	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);  in intel_dram_detect()
740 	drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",  in intel_dram_detect()
744 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)  in gen9_edram_size_mb()  argument
754 void intel_dram_edram_detect(struct drm_i915_private *i915)  in intel_dram_edram_detect()  argument
758 	if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))  in intel_dram_edram_detect()
761 	edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);  in intel_dram_edram_detect()
772 	if (GRAPHICS_VER(i915) < 9)  in intel_dram_edram_detect()
773 		i915->edram_size_mb = 128;  in intel_dram_edram_detect()
775 		i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);  in intel_dram_edram_detect()
777 	drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);  in intel_dram_edram_detect()