Lines Matching full:i915
43 void (*init_clock_gating)(struct drm_i915_private *i915);
46 static void gen9_init_clock_gating(struct drm_i915_private *i915) in gen9_init_clock_gating() argument
48 if (HAS_LLC(i915)) { in gen9_init_clock_gating()
56 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); in gen9_init_clock_gating()
60 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
63 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); in gen9_init_clock_gating()
69 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); in gen9_init_clock_gating()
72 static void bxt_init_clock_gating(struct drm_i915_private *i915) in bxt_init_clock_gating() argument
74 gen9_init_clock_gating(i915); in bxt_init_clock_gating()
77 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in bxt_init_clock_gating()
83 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); in bxt_init_clock_gating()
89 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, in bxt_init_clock_gating()
90 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
99 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); in bxt_init_clock_gating()
105 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in bxt_init_clock_gating()
108 static void glk_init_clock_gating(struct drm_i915_private *i915) in glk_init_clock_gating() argument
110 gen9_init_clock_gating(i915); in glk_init_clock_gating()
117 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, in glk_init_clock_gating()
118 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
122 static void ibx_init_clock_gating(struct drm_i915_private *i915) in ibx_init_clock_gating() argument
129 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
147 static void ilk_init_clock_gating(struct drm_i915_private *i915) in ilk_init_clock_gating() argument
159 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, in ilk_init_clock_gating()
162 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, in ilk_init_clock_gating()
172 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
173 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | in ilk_init_clock_gating()
176 intel_uncore_write(&i915->uncore, DISP_ARB_CTL, in ilk_init_clock_gating()
177 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | in ilk_init_clock_gating()
187 if (IS_IRONLAKE_M(i915)) { in ilk_init_clock_gating()
189 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); in ilk_init_clock_gating()
190 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); in ilk_init_clock_gating()
193 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); in ilk_init_clock_gating()
195 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); in ilk_init_clock_gating()
197 g4x_disable_trickle_feed(i915); in ilk_init_clock_gating()
199 ibx_init_clock_gating(i915); in ilk_init_clock_gating()
202 static void cpt_init_clock_gating(struct drm_i915_private *i915) in cpt_init_clock_gating() argument
212 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
215 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS); in cpt_init_clock_gating()
219 for_each_pipe(i915, pipe) { in cpt_init_clock_gating()
220 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
223 if (i915->display.vbt.fdi_rx_polarity_inverted) in cpt_init_clock_gating()
227 intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
230 for_each_pipe(i915, pipe) { in cpt_init_clock_gating()
231 intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
236 static void gen6_check_mch_setup(struct drm_i915_private *i915) in gen6_check_mch_setup() argument
240 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); in gen6_check_mch_setup()
242 drm_dbg_kms(&i915->drm, in gen6_check_mch_setup()
247 static void gen6_init_clock_gating(struct drm_i915_private *i915) in gen6_init_clock_gating() argument
251 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
253 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); in gen6_init_clock_gating()
255 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, in gen6_init_clock_gating()
256 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | in gen6_init_clock_gating()
273 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, in gen6_init_clock_gating()
288 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
289 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | in gen6_init_clock_gating()
291 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
292 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
294 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
295 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | in gen6_init_clock_gating()
299 g4x_disable_trickle_feed(i915); in gen6_init_clock_gating()
301 cpt_init_clock_gating(i915); in gen6_init_clock_gating()
303 gen6_check_mch_setup(i915); in gen6_init_clock_gating()
306 static void lpt_init_clock_gating(struct drm_i915_private *i915) in lpt_init_clock_gating() argument
312 if (HAS_PCH_LPT_LP(i915)) in lpt_init_clock_gating()
313 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
317 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
321 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, in gen8_set_l3sqc_credits() argument
329 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, in gen8_set_l3sqc_credits()
332 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
336 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val); in gen8_set_l3sqc_credits()
342 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
344 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); in gen8_set_l3sqc_credits()
347 static void dg2_init_clock_gating(struct drm_i915_private *i915) in dg2_init_clock_gating() argument
350 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, in dg2_init_clock_gating()
354 static void cnp_init_clock_gating(struct drm_i915_private *i915) in cnp_init_clock_gating() argument
356 if (!HAS_PCH_CNP(i915)) in cnp_init_clock_gating()
360 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE); in cnp_init_clock_gating()
363 static void cfl_init_clock_gating(struct drm_i915_private *i915) in cfl_init_clock_gating() argument
365 cnp_init_clock_gating(i915); in cfl_init_clock_gating()
366 gen9_init_clock_gating(i915); in cfl_init_clock_gating()
369 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); in cfl_init_clock_gating()
375 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in cfl_init_clock_gating()
378 static void kbl_init_clock_gating(struct drm_i915_private *i915) in kbl_init_clock_gating() argument
380 gen9_init_clock_gating(i915); in kbl_init_clock_gating()
383 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); in kbl_init_clock_gating()
386 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) in kbl_init_clock_gating()
387 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, in kbl_init_clock_gating()
391 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) in kbl_init_clock_gating()
392 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, in kbl_init_clock_gating()
399 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in kbl_init_clock_gating()
402 static void skl_init_clock_gating(struct drm_i915_private *i915) in skl_init_clock_gating() argument
404 gen9_init_clock_gating(i915); in skl_init_clock_gating()
407 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, in skl_init_clock_gating()
411 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); in skl_init_clock_gating()
417 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in skl_init_clock_gating()
420 static void bdw_init_clock_gating(struct drm_i915_private *i915) in bdw_init_clock_gating() argument
425 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in bdw_init_clock_gating()
428 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); in bdw_init_clock_gating()
431 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); in bdw_init_clock_gating()
433 for_each_pipe(i915, pipe) { in bdw_init_clock_gating()
435 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), in bdw_init_clock_gating()
441 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, in bdw_init_clock_gating()
444 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in bdw_init_clock_gating()
448 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in bdw_init_clock_gating()
451 gen8_set_l3sqc_credits(i915, 30, 2); in bdw_init_clock_gating()
454 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, in bdw_init_clock_gating()
457 lpt_init_clock_gating(i915); in bdw_init_clock_gating()
464 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); in bdw_init_clock_gating()
467 static void hsw_init_clock_gating(struct drm_i915_private *i915) in hsw_init_clock_gating() argument
472 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in hsw_init_clock_gating()
475 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); in hsw_init_clock_gating()
477 for_each_pipe(i915, pipe) { in hsw_init_clock_gating()
479 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), in hsw_init_clock_gating()
484 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in hsw_init_clock_gating()
488 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); in hsw_init_clock_gating()
490 lpt_init_clock_gating(i915); in hsw_init_clock_gating()
493 static void ivb_init_clock_gating(struct drm_i915_private *i915) in ivb_init_clock_gating() argument
495 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivb_init_clock_gating()
498 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); in ivb_init_clock_gating()
501 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, in ivb_init_clock_gating()
505 if (INTEL_INFO(i915)->gt == 1) in ivb_init_clock_gating()
506 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
510 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
512 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, in ivb_init_clock_gating()
520 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, in ivb_init_clock_gating()
524 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivb_init_clock_gating()
527 g4x_disable_trickle_feed(i915); in ivb_init_clock_gating()
529 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, in ivb_init_clock_gating()
532 if (!HAS_PCH_NOP(i915)) in ivb_init_clock_gating()
533 cpt_init_clock_gating(i915); in ivb_init_clock_gating()
535 gen6_check_mch_setup(i915); in ivb_init_clock_gating()
538 static void vlv_init_clock_gating(struct drm_i915_private *i915) in vlv_init_clock_gating() argument
541 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, in vlv_init_clock_gating()
546 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, in vlv_init_clock_gating()
550 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in vlv_init_clock_gating()
557 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, in vlv_init_clock_gating()
563 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); in vlv_init_clock_gating()
570 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in vlv_init_clock_gating()
573 static void chv_init_clock_gating(struct drm_i915_private *i915) in chv_init_clock_gating() argument
577 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, in chv_init_clock_gating()
581 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in chv_init_clock_gating()
585 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); in chv_init_clock_gating()
588 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in chv_init_clock_gating()
595 gen8_set_l3sqc_credits(i915, 38, 2); in chv_init_clock_gating()
598 static void g4x_init_clock_gating(struct drm_i915_private *i915) in g4x_init_clock_gating() argument
602 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
603 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
606 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
610 if (IS_GM45(i915)) in g4x_init_clock_gating()
612 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate); in g4x_init_clock_gating()
614 g4x_disable_trickle_feed(i915); in g4x_init_clock_gating()
617 static void i965gm_init_clock_gating(struct drm_i915_private *i915) in i965gm_init_clock_gating() argument
619 struct intel_uncore *uncore = &i915->uncore; in i965gm_init_clock_gating()
623 intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0); in i965gm_init_clock_gating()
631 static void i965g_init_clock_gating(struct drm_i915_private *i915) in i965g_init_clock_gating() argument
633 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in i965g_init_clock_gating()
638 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); in i965g_init_clock_gating()
639 intel_uncore_write(&i915->uncore, MI_ARB_STATE, in i965g_init_clock_gating()
643 static void gen3_init_clock_gating(struct drm_i915_private *i915) in gen3_init_clock_gating() argument
645 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE); in gen3_init_clock_gating()
649 intel_uncore_write(&i915->uncore, D_STATE, dstate); in gen3_init_clock_gating()
651 if (IS_PINEVIEW(i915)) in gen3_init_clock_gating()
652 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
656 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
660 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
663 intel_uncore_write(&i915->uncore, MI_ARB_STATE, in gen3_init_clock_gating()
666 intel_uncore_write(&i915->uncore, MI_ARB_STATE, in gen3_init_clock_gating()
670 static void i85x_init_clock_gating(struct drm_i915_private *i915) in i85x_init_clock_gating() argument
672 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
675 intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
678 intel_uncore_write(&i915->uncore, MEM_MODE, in i85x_init_clock_gating()
688 intel_uncore_write(&i915->uncore, SCPD0, in i85x_init_clock_gating()
692 static void i830_init_clock_gating(struct drm_i915_private *i915) in i830_init_clock_gating() argument
694 intel_uncore_write(&i915->uncore, MEM_MODE, in i830_init_clock_gating()
699 void intel_clock_gating_init(struct drm_i915_private *i915) in intel_clock_gating_init() argument
701 i915->clock_gating_funcs->init_clock_gating(i915); in intel_clock_gating_init()
704 static void nop_init_clock_gating(struct drm_i915_private *i915) in nop_init_clock_gating() argument
706 drm_dbg_kms(&i915->drm, in nop_init_clock_gating()
739 * @i915: device private
746 void intel_clock_gating_hooks_init(struct drm_i915_private *i915) in intel_clock_gating_hooks_init() argument
748 if (IS_DG2(i915)) in intel_clock_gating_hooks_init()
749 i915->clock_gating_funcs = &dg2_clock_gating_funcs; in intel_clock_gating_hooks_init()
750 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) in intel_clock_gating_hooks_init()
751 i915->clock_gating_funcs = &cfl_clock_gating_funcs; in intel_clock_gating_hooks_init()
752 else if (IS_SKYLAKE(i915)) in intel_clock_gating_hooks_init()
753 i915->clock_gating_funcs = &skl_clock_gating_funcs; in intel_clock_gating_hooks_init()
754 else if (IS_KABYLAKE(i915)) in intel_clock_gating_hooks_init()
755 i915->clock_gating_funcs = &kbl_clock_gating_funcs; in intel_clock_gating_hooks_init()
756 else if (IS_BROXTON(i915)) in intel_clock_gating_hooks_init()
757 i915->clock_gating_funcs = &bxt_clock_gating_funcs; in intel_clock_gating_hooks_init()
758 else if (IS_GEMINILAKE(i915)) in intel_clock_gating_hooks_init()
759 i915->clock_gating_funcs = &glk_clock_gating_funcs; in intel_clock_gating_hooks_init()
760 else if (IS_BROADWELL(i915)) in intel_clock_gating_hooks_init()
761 i915->clock_gating_funcs = &bdw_clock_gating_funcs; in intel_clock_gating_hooks_init()
762 else if (IS_CHERRYVIEW(i915)) in intel_clock_gating_hooks_init()
763 i915->clock_gating_funcs = &chv_clock_gating_funcs; in intel_clock_gating_hooks_init()
764 else if (IS_HASWELL(i915)) in intel_clock_gating_hooks_init()
765 i915->clock_gating_funcs = &hsw_clock_gating_funcs; in intel_clock_gating_hooks_init()
766 else if (IS_IVYBRIDGE(i915)) in intel_clock_gating_hooks_init()
767 i915->clock_gating_funcs = &ivb_clock_gating_funcs; in intel_clock_gating_hooks_init()
768 else if (IS_VALLEYVIEW(i915)) in intel_clock_gating_hooks_init()
769 i915->clock_gating_funcs = &vlv_clock_gating_funcs; in intel_clock_gating_hooks_init()
770 else if (GRAPHICS_VER(i915) == 6) in intel_clock_gating_hooks_init()
771 i915->clock_gating_funcs = &gen6_clock_gating_funcs; in intel_clock_gating_hooks_init()
772 else if (GRAPHICS_VER(i915) == 5) in intel_clock_gating_hooks_init()
773 i915->clock_gating_funcs = &ilk_clock_gating_funcs; in intel_clock_gating_hooks_init()
774 else if (IS_G4X(i915)) in intel_clock_gating_hooks_init()
775 i915->clock_gating_funcs = &g4x_clock_gating_funcs; in intel_clock_gating_hooks_init()
776 else if (IS_I965GM(i915)) in intel_clock_gating_hooks_init()
777 i915->clock_gating_funcs = &i965gm_clock_gating_funcs; in intel_clock_gating_hooks_init()
778 else if (IS_I965G(i915)) in intel_clock_gating_hooks_init()
779 i915->clock_gating_funcs = &i965g_clock_gating_funcs; in intel_clock_gating_hooks_init()
780 else if (GRAPHICS_VER(i915) == 3) in intel_clock_gating_hooks_init()
781 i915->clock_gating_funcs = &gen3_clock_gating_funcs; in intel_clock_gating_hooks_init()
782 else if (IS_I85X(i915) || IS_I865G(i915)) in intel_clock_gating_hooks_init()
783 i915->clock_gating_funcs = &i85x_clock_gating_funcs; in intel_clock_gating_hooks_init()
784 else if (GRAPHICS_VER(i915) == 2) in intel_clock_gating_hooks_init()
785 i915->clock_gating_funcs = &i830_clock_gating_funcs; in intel_clock_gating_hooks_init()
787 i915->clock_gating_funcs = &nop_clock_gating_funcs; in intel_clock_gating_hooks_init()