153 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,  in intel_vgpu_get_stride()  argument
156 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_get_stride()
159 	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;  in intel_vgpu_get_stride()
190 static int get_active_pipe(struct intel_vgpu *vgpu)  in get_active_pipe()  argument
195 		if (pipe_is_enabled(vgpu, i))  in get_active_pipe()
203  * @vgpu: input vgpu
210 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,  in intel_vgpu_decode_primary_plane()  argument
213 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_decode_primary_plane()
218 	pipe = get_active_pipe(vgpu);  in intel_vgpu_decode_primary_plane()
222 	val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));  in intel_vgpu_decode_primary_plane()
256 	plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_primary_plane()
257 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_primary_plane()
260 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_primary_plane()
267 	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,  in intel_vgpu_decode_primary_plane()
272 	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>  in intel_vgpu_decode_primary_plane()
275 	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &  in intel_vgpu_decode_primary_plane()
279 	val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));  in intel_vgpu_decode_primary_plane()
334  * @vgpu: input vgpu
341 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,  in intel_vgpu_decode_cursor_plane()  argument
344 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_decode_cursor_plane()
350 	pipe = get_active_pipe(vgpu);  in intel_vgpu_decode_cursor_plane()
354 	val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));  in intel_vgpu_decode_cursor_plane()
380 	plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_cursor_plane()
381 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_cursor_plane()
384 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_cursor_plane()
391 	val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));  in intel_vgpu_decode_cursor_plane()
397 	plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));  in intel_vgpu_decode_cursor_plane()
398 	plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));  in intel_vgpu_decode_cursor_plane()
414  * @vgpu: input vgpu
421 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,  in intel_vgpu_decode_sprite_plane()  argument
429 	pipe = get_active_pipe(vgpu);  in intel_vgpu_decode_sprite_plane()
433 	val = vgpu_vreg_t(vgpu, SPRCTL(pipe));  in intel_vgpu_decode_sprite_plane()
484 	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_sprite_plane()
485 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_sprite_plane()
488 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_sprite_plane()
495 	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &  in intel_vgpu_decode_sprite_plane()
498 	val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));  in intel_vgpu_decode_sprite_plane()
506 	val = vgpu_vreg_t(vgpu, SPRPOS(pipe));  in intel_vgpu_decode_sprite_plane()
510 	val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));  in intel_vgpu_decode_sprite_plane()