Lines Matching +full:charge +full:- +full:ctrl +full:- +full:value
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
56 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; in edid_get_byte()
59 if (edid->state == I2C_NOT_SPECIFIED || !edid->target_selected) { in edid_get_byte()
63 if (edid->current_edid_read >= EDID_SIZE) { in edid_get_byte()
68 if (!edid->edid_available) { in edid_get_byte()
73 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) { in edid_get_byte()
75 intel_vgpu_port(vgpu, edid->port)->edid; in edid_get_byte()
77 chr = edid_data->edid_block[edid->current_edid_read]; in edid_get_byte()
78 edid->current_edid_read++; in edid_get_byte()
88 int port = -EINVAL; in cnp_get_port_from_gmbus0()
104 int port = -EINVAL; in bxt_get_port_from_gmbus0()
118 int port = -EINVAL; in get_port_from_gmbus0()
134 if (!vgpu->display.i2c_edid.edid_available) in reset_gmbus_controller()
136 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; in reset_gmbus_controller()
143 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gmbus0_mmio_write()
161 if (drm_WARN_ON(&i915->drm, port < 0)) in gmbus0_mmio_write()
164 vgpu->display.i2c_edid.state = I2C_GMBUS; in gmbus0_mmio_write()
165 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; in gmbus0_mmio_write()
172 vgpu->display.i2c_edid.port = port; in gmbus0_mmio_write()
173 vgpu->display.i2c_edid.edid_available = true; in gmbus0_mmio_write()
183 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; in gmbus1_mmio_write()
213 i2c_edid->gmbus.total_byte_count = in gmbus1_mmio_write()
219 i2c_edid->target_selected = true; in gmbus1_mmio_write()
224 vgpu->id, target_addr); in gmbus1_mmio_write()
228 i2c_edid->current_edid_read = in gmbus1_mmio_write()
231 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue); in gmbus1_mmio_write()
251 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; in gmbus1_mmio_write()
261 * START (-->INDEX) -->DATA in gmbus1_mmio_write()
263 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE; in gmbus1_mmio_write()
284 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in gmbus3_mmio_write()
286 drm_WARN_ON(&i915->drm, 1); in gmbus3_mmio_write()
295 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; in gmbus3_mmio_read()
296 int byte_left = i2c_edid->gmbus.total_byte_count - in gmbus3_mmio_read()
297 i2c_edid->current_edid_read; in gmbus3_mmio_read()
319 switch (i2c_edid->gmbus.cycle_type) { in gmbus3_mmio_read()
322 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; in gmbus3_mmio_read()
327 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE; in gmbus3_mmio_read()
334 * return the latest written value in gmbus3_mmio_read()
346 u32 value = vgpu_vreg(vgpu, offset); in gmbus2_mmio_read() local
350 memcpy(p_data, (void *)&value, bytes); in gmbus2_mmio_read()
361 /* All other bits are read-only */ in gmbus2_mmio_write()
366 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
381 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_gmbus_read()
383 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1)))) in intel_gvt_i2c_handle_gmbus_read()
384 return -EINVAL; in intel_gvt_i2c_handle_gmbus_read()
396 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
411 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_gmbus_write()
413 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1)))) in intel_gvt_i2c_handle_gmbus_write()
414 return -EINVAL; in intel_gvt_i2c_handle_gmbus_write()
462 reg = -1; in get_aux_ch_reg()
469 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
483 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_gvt_i2c_handle_aux_ch_write()
484 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; in intel_gvt_i2c_handle_aux_ch_write()
486 int msg, addr, ctrl, op; in intel_gvt_i2c_handle_aux_ch_write() local
487 u32 value = *(u32 *)p_data; in intel_gvt_i2c_handle_aux_ch_write() local
492 vgpu_vreg(vgpu, offset) = value; in intel_gvt_i2c_handle_aux_ch_write()
496 msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value); in intel_gvt_i2c_handle_aux_ch_write()
501 ctrl = (msg >> 24) & 0xff; in intel_gvt_i2c_handle_aux_ch_write()
502 op = ctrl >> 4; in intel_gvt_i2c_handle_aux_ch_write()
503 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) { in intel_gvt_i2c_handle_aux_ch_write()
508 /* Always set the wanted value for vms. */ in intel_gvt_i2c_handle_aux_ch_write()
520 i2c_edid->aux_ch.i2c_over_aux_ch = true; in intel_gvt_i2c_handle_aux_ch_write()
521 i2c_edid->aux_ch.aux_ch_mot = true; in intel_gvt_i2c_handle_aux_ch_write()
526 i2c_edid->state = I2C_AUX_CH; in intel_gvt_i2c_handle_aux_ch_write()
527 i2c_edid->port = port_idx; in intel_gvt_i2c_handle_aux_ch_write()
528 i2c_edid->target_selected = true; in intel_gvt_i2c_handle_aux_ch_write()
532 i2c_edid->edid_available = true; in intel_gvt_i2c_handle_aux_ch_write()
543 if (drm_WARN_ON(&i915->drm, (op & 0x1) != DP_AUX_I2C_READ)) in intel_gvt_i2c_handle_aux_ch_write()
545 if (drm_WARN_ON(&i915->drm, msg_length != 4)) in intel_gvt_i2c_handle_aux_ch_write()
547 if (i2c_edid->edid_available && i2c_edid->target_selected) { in intel_gvt_i2c_handle_aux_ch_write()
554 /* write the return value in AUX_CH_DATA reg which includes: in intel_gvt_i2c_handle_aux_ch_write()
563 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
571 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; in intel_vgpu_init_i2c_edid()
573 edid->state = I2C_NOT_SPECIFIED; in intel_vgpu_init_i2c_edid()
575 edid->port = -1; in intel_vgpu_init_i2c_edid()
576 edid->target_selected = false; in intel_vgpu_init_i2c_edid()
577 edid->edid_available = false; in intel_vgpu_init_i2c_edid()
578 edid->current_edid_read = 0; in intel_vgpu_init_i2c_edid()
580 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus)); in intel_vgpu_init_i2c_edid()
582 edid->aux_ch.i2c_over_aux_ch = false; in intel_vgpu_init_i2c_edid()
583 edid->aux_ch.aux_ch_mot = false; in intel_vgpu_init_i2c_edid()