Lines Matching full:vgpu
49 static int get_edp_pipe(struct intel_vgpu *vgpu) in get_edp_pipe() argument
51 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe()
69 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) in edp_pipe_is_enabled() argument
71 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in edp_pipe_is_enabled()
74 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
77 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled()
82 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) in pipe_is_enabled() argument
84 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in pipe_is_enabled()
91 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled()
94 if (edp_pipe_is_enabled(vgpu) && in pipe_is_enabled()
95 get_edp_pipe(vgpu) == pipe) in pipe_is_enabled()
183 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) in emulate_monitor_status_change() argument
185 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_monitor_status_change()
194 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in emulate_monitor_status_change()
200 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= in emulate_monitor_status_change()
202 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
203 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
204 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
205 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
209 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= in emulate_monitor_status_change()
213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
218 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= in emulate_monitor_status_change()
220 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= in emulate_monitor_status_change()
224 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= in emulate_monitor_status_change()
229 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= in emulate_monitor_status_change()
232 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
234 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
236 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
238 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in emulate_monitor_status_change()
240 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ in emulate_monitor_status_change()
241 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; in emulate_monitor_status_change()
242 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; in emulate_monitor_status_change()
244 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); in emulate_monitor_status_change()
245 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
247 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in emulate_monitor_status_change()
249 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
250 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); in emulate_monitor_status_change()
252 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
253 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
256 * Only 1 PIPE enabled in current vGPU display and PIPE_A is in emulate_monitor_status_change()
261 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
262 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; in emulate_monitor_status_change()
270 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
271 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
272 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
274 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
277 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
278 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); in emulate_monitor_status_change()
279 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in emulate_monitor_status_change()
281 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= in emulate_monitor_status_change()
283 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in emulate_monitor_status_change()
285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in emulate_monitor_status_change()
288 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= in emulate_monitor_status_change()
292 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
294 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
296 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
300 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
302 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
306 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in emulate_monitor_status_change()
307 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
308 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); in emulate_monitor_status_change()
309 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
311 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
313 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
318 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= in emulate_monitor_status_change()
322 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
326 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
331 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
333 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
337 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { in emulate_monitor_status_change()
338 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
339 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); in emulate_monitor_status_change()
340 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
342 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
344 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in emulate_monitor_status_change()
346 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in emulate_monitor_status_change()
349 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= in emulate_monitor_status_change()
353 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
355 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
357 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
362 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in emulate_monitor_status_change()
364 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
371 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | in emulate_monitor_status_change()
379 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | in emulate_monitor_status_change()
381 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= in emulate_monitor_status_change()
387 * Only 1 PIPE enabled in current vGPU display and PIPE_A is in emulate_monitor_status_change()
394 vgpu_vreg_t(vgpu, DPLL_CTRL1) = in emulate_monitor_status_change()
396 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= in emulate_monitor_status_change()
398 vgpu_vreg_t(vgpu, LCPLL1_CTL) = in emulate_monitor_status_change()
400 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); in emulate_monitor_status_change()
407 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
408 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
409 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
410 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
411 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
414 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in emulate_monitor_status_change()
415 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
417 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
419 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
421 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; in emulate_monitor_status_change()
422 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
425 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
430 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
432 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= in emulate_monitor_status_change()
435 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
436 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
437 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; in emulate_monitor_status_change()
440 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { in emulate_monitor_status_change()
441 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
443 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
445 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
447 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; in emulate_monitor_status_change()
448 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
451 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
456 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= in emulate_monitor_status_change()
458 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= in emulate_monitor_status_change()
461 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
462 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
463 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; in emulate_monitor_status_change()
466 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { in emulate_monitor_status_change()
467 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
469 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
471 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
473 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; in emulate_monitor_status_change()
474 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
477 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
482 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= in emulate_monitor_status_change()
484 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= in emulate_monitor_status_change()
487 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
488 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
489 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; in emulate_monitor_status_change()
496 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { in emulate_monitor_status_change()
497 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; in emulate_monitor_status_change()
500 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
502 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in emulate_monitor_status_change()
505 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; in emulate_monitor_status_change()
507 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
512 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; in emulate_monitor_status_change()
516 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
517 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
518 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
519 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
522 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
525 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) in clean_virtual_dp_monitor() argument
527 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); in clean_virtual_dp_monitor()
539 struct intel_vgpu *vgpu; in vblank_timer_fn() local
542 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); in vblank_timer_fn()
544 /* Set vblank emulation request per-vGPU bit */ in vblank_timer_fn()
545 intel_gvt_request_service(vgpu->gvt, in vblank_timer_fn()
546 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); in vblank_timer_fn()
551 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, in setup_virtual_dp_monitor() argument
554 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in setup_virtual_dp_monitor()
555 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); in setup_virtual_dp_monitor()
556 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; in setup_virtual_dp_monitor()
581 vgpu->display.port_num = port_num; in setup_virtual_dp_monitor()
589 emulate_monitor_status_change(vgpu); in setup_virtual_dp_monitor()
595 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
596 * @vgpu: vGPU operated
599 * This function is used to turn on/off or update the per-vGPU vblank_timer
604 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) in vgpu_update_vblank_emulation() argument
606 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; in vgpu_update_vblank_emulation()
608 intel_vgpu_port(vgpu, vgpu->display.port_num); in vgpu_update_vblank_emulation()
635 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) in emulate_vblank_on_pipe() argument
637 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_vblank_on_pipe()
639 struct intel_vgpu_irq *irq = &vgpu->irq; in emulate_vblank_on_pipe()
653 if (!pipe_is_enabled(vgpu, pipe)) in emulate_vblank_on_pipe()
656 intel_vgpu_trigger_virtual_event(vgpu, event); in emulate_vblank_on_pipe()
659 if (pipe_is_enabled(vgpu, pipe)) { in emulate_vblank_on_pipe()
660 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++; in emulate_vblank_on_pipe()
661 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); in emulate_vblank_on_pipe()
665 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) in intel_vgpu_emulate_vblank() argument
667 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_vblank()
671 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
673 emulate_vblank_on_pipe(vgpu, pipe); in intel_vgpu_emulate_vblank()
674 mutex_unlock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
678 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
679 * @vgpu: a vGPU
682 * This function is used to trigger hotplug interrupt for vGPU
685 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) in intel_vgpu_emulate_hotplug() argument
687 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_hotplug()
695 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
697 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
699 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
701 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
703 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; in intel_vgpu_emulate_hotplug()
704 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
706 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); in intel_vgpu_emulate_hotplug()
708 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in intel_vgpu_emulate_hotplug()
710 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
713 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
718 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
720 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
722 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); in intel_vgpu_emulate_hotplug()
724 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { in intel_vgpu_emulate_hotplug()
726 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
728 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
731 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
733 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
736 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
738 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
740 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
742 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); in intel_vgpu_emulate_hotplug()
744 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { in intel_vgpu_emulate_hotplug()
746 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= in intel_vgpu_emulate_hotplug()
748 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= in intel_vgpu_emulate_hotplug()
751 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= in intel_vgpu_emulate_hotplug()
753 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= in intel_vgpu_emulate_hotplug()
756 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= in intel_vgpu_emulate_hotplug()
758 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= in intel_vgpu_emulate_hotplug()
760 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= in intel_vgpu_emulate_hotplug()
762 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); in intel_vgpu_emulate_hotplug()
768 * intel_vgpu_clean_display - clean vGPU virtual display emulation
769 * @vgpu: a vGPU
771 * This function is used to clean vGPU virtual display emulation stuffs
774 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) in intel_vgpu_clean_display() argument
776 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_clean_display()
782 clean_virtual_dp_monitor(vgpu, PORT_D); in intel_vgpu_clean_display()
784 clean_virtual_dp_monitor(vgpu, PORT_B); in intel_vgpu_clean_display()
786 vgpu_update_vblank_emulation(vgpu, false); in intel_vgpu_clean_display()
790 * intel_vgpu_init_display- initialize vGPU virtual display emulation
791 * @vgpu: a vGPU
794 * This function is used to initialize vGPU virtual display emulation stuffs
800 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) in intel_vgpu_init_display() argument
802 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_init_display()
804 intel_vgpu_init_i2c_edid(vgpu); in intel_vgpu_init_display()
810 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, in intel_vgpu_init_display()
813 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, in intel_vgpu_init_display()
818 * intel_vgpu_reset_display- reset vGPU virtual display emulation
819 * @vgpu: a vGPU
821 * This function is used to reset vGPU virtual display emulation stuffs
824 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) in intel_vgpu_reset_display() argument
826 emulate_monitor_status_change(vgpu); in intel_vgpu_reset_display()