38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)  in intel_sseu_get_hsw_subslices()  argument
41 	if (WARN_ON(slice >= sseu->max_slices))  in intel_sseu_get_hsw_subslices()
44 	return sseu->subslice_mask.hsw[slice];  in intel_sseu_get_hsw_subslices()
47 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,  in sseu_get_eus()  argument
51 		WARN_ON(slice > 0);  in sseu_get_eus()
54 		return sseu->eu_mask.hsw[slice][subslice];  in sseu_get_eus()
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,  in sseu_set_eus()  argument
63 		GEM_WARN_ON(slice > 0);  in sseu_set_eus()
66 		sseu->eu_mask.hsw[slice][subslice] = eu_mask;  in sseu_set_eus()
221 	 * The concept of slice has been removed in Xe_HP.  To be compatible  in xehp_sseu_info_init()
222 	 * with prior generations, assume a single slice across the entire  in xehp_sseu_info_init()
224 	 * that software slice.  in xehp_sseu_info_init()
270 	 * DG1, and ADL only had a single slice.  in gen12_sseu_info_init()
288 	/* TGL only supports slice-level power gating */  in gen12_sseu_info_init()
307 	 * EHL/JSL only had a single slice in practice.  in gen11_sseu_info_init()
390 	/* BXT has a single slice and at most 3 subslices. */  in gen9_sseu_info_init()
408 			/* skip disabled slice */  in gen9_sseu_info_init()
454 	 * SKL+ supports slice power gating on devices with more than  in gen9_sseu_info_init()
455 	 * one slice, and supports EU power gating on devices with  in gen9_sseu_info_init()
520 			/* skip disabled slice */  in bdw_sseu_info_init()
561 	 * BDW supports slice power gating on devices with more than  in bdw_sseu_info_init()
562 	 * one slice.  in bdw_sseu_info_init()
667 	 * slice/subslice/EU enablement prior to Gen9.  in intel_sseu_make_rpcs()
698 	 * When more than one slice is enabled, hardware ignores the subslice  in intel_sseu_make_rpcs()
705 	 * slice.  in intel_sseu_make_rpcs()
718 	 * slice/subslice/EU in a partially enabled state. We  in intel_sseu_make_rpcs()
785 		drm_printf(p, "slice total: %u, mask=%04x\n",  in intel_sseu_dump()
793 			drm_printf(p, "slice%d: %u subslices, mask=%08x\n",  in intel_sseu_dump()
800 	drm_printf(p, "has slice power gating: %s\n",  in intel_sseu_dump()
816 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",  in sseu_print_hsw_topology()
870 			seq_printf(m, "  %s Slice%i subslices: %u\n", type,  in intel_sseu_print_ss_info()