Lines Matching +full:wakeup +full:- +full:latency
1 // SPDX-License-Identifier: MIT
24 * low-voltage mode when idle, using down to 0V while at this stage. This
30 * among each other with the latency required to enter and leave RC6 and
38 * require higher latency to switch to and wake up.
48 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
53 return rc6_to_gt(rc)->i915; in rc6_to_i915()
59 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable()
68 if (!intel_uc_uses_guc_rc(>->uc)) { in gen11_rc6_enable()
76 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
90 * it takes us to service a CS interrupt and submit a new ELSP - that in gen11_rc6_enable()
93 * interrupt service latency, the hardware will automatically gate in gen11_rc6_enable()
95 * the service latency. A similar guide from plane_state is that we in gen11_rc6_enable()
96 * do not want the enable hysteresis to less than the wakeup latency. in gen11_rc6_enable()
99 * service latency, and puts it under 10us for Icelake, similar to in gen11_rc6_enable()
113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; in gen11_rc6_enable()
115 rc6->ctl_enable = in gen11_rc6_enable()
125 if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) { in gen11_rc6_enable()
158 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen9_rc6_enable()
169 * it takes us to service a CS interrupt and submit a new ELSP - that in gen9_rc6_enable()
172 * interrupt service latency, the hardware will automatically gate in gen9_rc6_enable()
174 * the service latency. A similar guide from plane_state is that we in gen9_rc6_enable()
175 * do not want the enable hysteresis to less than the wakeup latency. in gen9_rc6_enable()
178 * service latency, and puts it around 10us for Broadwell (and other in gen9_rc6_enable()
181 * However, the wakeup latency on Broxton is closer to 100us. To be in gen9_rc6_enable()
191 rc6->ctl_enable = in gen9_rc6_enable()
198 * - Render/Media PG need to be disabled with RC6. in gen9_rc6_enable()
216 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen8_rc6_enable()
221 rc6->ctl_enable = in gen8_rc6_enable()
243 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen6_rc6_enable()
257 rc6->ctl_enable = in gen6_rc6_enable()
263 ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); in gen6_rc6_enable()
265 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); in gen6_rc6_enable()
268 drm_dbg(&i915->drm, in gen6_rc6_enable()
269 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", in gen6_rc6_enable()
273 ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); in gen6_rc6_enable()
275 drm_err(&i915->drm, in gen6_rc6_enable()
291 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); in chv_rc6_init()
292 paddr = i915->dsm.stolen.end + 1 - pctx_size; in chv_rc6_init()
313 /* BIOS set it up already, grab the pre-alloc'd space */ in vlv_rc6_init()
316 pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start; in vlv_rc6_init()
317 pctx = i915_gem_object_create_region_at(i915->mm.stolen_region, in vlv_rc6_init()
327 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); in vlv_rc6_init()
339 drm_dbg(&i915->drm, in vlv_rc6_init()
345 i915->dsm.stolen.start, in vlv_rc6_init()
346 pctx->stolen->start, in vlv_rc6_init()
348 pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start; in vlv_rc6_init()
352 rc6->pctx = pctx; in vlv_rc6_init()
368 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in chv_rc6_enable()
381 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; in chv_rc6_enable()
395 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in vlv_rc6_enable()
407 rc6->ctl_enable = in vlv_rc6_enable()
413 if (!rc6->bios_state_captured) { in intel_check_bios_c6_setup()
417 with_intel_runtime_pm(uncore->rpm, wakeref) in intel_check_bios_c6_setup()
418 rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE); in intel_check_bios_c6_setup()
420 rc6->bios_state_captured = true; in intel_check_bios_c6_setup()
423 return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK; in intel_check_bios_c6_setup()
437 drm_dbg(&i915->drm, "BIOS enabled RC states: " in bxt_check_bios_rc6_setup()
444 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); in bxt_check_bios_rc6_setup()
454 if (!(rc6_ctx_base >= i915->dsm.reserved.start && in bxt_check_bios_rc6_setup()
455 rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) { in bxt_check_bios_rc6_setup()
456 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); in bxt_check_bios_rc6_setup()
464 drm_dbg(&i915->drm, in bxt_check_bios_rc6_setup()
472 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); in bxt_check_bios_rc6_setup()
477 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); in bxt_check_bios_rc6_setup()
482 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); in bxt_check_bios_rc6_setup()
504 drm_notice(&i915->drm, in rc6_supported()
509 if (IS_METEORLAKE(gt->i915) && in rc6_supported()
511 drm_notice(&i915->drm, in rc6_supported()
517 drm_notice(&i915->drm, in rc6_supported()
527 GEM_BUG_ON(rc6->wakeref); in rpm_get()
528 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); in rpm_get()
529 rc6->wakeref = true; in rpm_get()
534 GEM_BUG_ON(!rc6->wakeref); in rpm_put()
535 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); in rpm_put()
536 rc6->wakeref = false; in rpm_put()
549 drm_notice(&i915->drm, in pctx_corrupted()
574 [0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG, in rc6_res_reg_init()
577 switch (rc6_to_gt(rc6)->type) { in rc6_res_reg_init()
589 memcpy(rc6->res_reg, res_reg, sizeof(res_reg)); in rc6_res_reg_init()
597 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ in intel_rc6_init()
615 rc6->supported = err == 0; in intel_rc6_init()
620 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); in intel_rc6_sanitize()
622 if (rc6->enabled) { /* unbalanced suspend/resume */ in intel_rc6_sanitize()
624 rc6->enabled = false; in intel_rc6_sanitize()
627 if (rc6->supported) in intel_rc6_sanitize()
636 if (!rc6->supported) in intel_rc6_enable()
639 GEM_BUG_ON(rc6->enabled); in intel_rc6_enable()
656 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; in intel_rc6_enable()
658 rc6->ctl_enable = 0; in intel_rc6_enable()
665 /* rc6 is ready, runtime-pm is go! */ in intel_rc6_enable()
667 rc6->enabled = true; in intel_rc6_enable()
674 if (!rc6->enabled) in intel_rc6_unpark()
678 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); in intel_rc6_unpark()
686 if (!rc6->enabled) in intel_rc6_park()
694 if (!rc6->manual) in intel_rc6_park()
711 if (!rc6->enabled) in intel_rc6_disable()
715 rc6->enabled = false; in intel_rc6_disable()
728 if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured) in intel_rc6_fini()
729 intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state); in intel_rc6_fini()
731 pctx = fetch_and_zero(&rc6->pctx); in intel_rc6_fini()
735 if (rc6->wakeref) in intel_rc6_fini()
748 lockdep_assert_held(&uncore->lock); in vlv_residency_raw()
755 * Although we always use the counter in high-range mode elsewhere, in vlv_residency_raw()
773 } while (upper != tmp && --loop); in vlv_residency_raw()
777 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set in vlv_residency_raw()
789 i915_reg_t reg = rc6->res_reg[id]; in intel_rc6_residency_ns()
794 if (!rc6->supported) in intel_rc6_residency_ns()
799 spin_lock_irqsave(&uncore->lock, flags); in intel_rc6_residency_ns()
805 div = i915->czclk_freq; in intel_rc6_residency_ns()
825 * Store previous hw counter values for counter wrap-around handling. But in intel_rc6_residency_ns()
828 prev_hw = rc6->prev_hw_residency[id]; in intel_rc6_residency_ns()
829 rc6->prev_hw_residency[id] = time_hw; in intel_rc6_residency_ns()
833 time_hw -= prev_hw; in intel_rc6_residency_ns()
835 time_hw += overflow_hw - prev_hw; in intel_rc6_residency_ns()
838 time_hw += rc6->cur_residency[id]; in intel_rc6_residency_ns()
839 rc6->cur_residency[id] = time_hw; in intel_rc6_residency_ns()
842 spin_unlock_irqrestore(&uncore->lock, flags); in intel_rc6_residency_ns()
855 struct intel_gt *gt = m->private; in intel_rc6_print_residency()
856 i915_reg_t reg = gt->rc6.res_reg[id]; in intel_rc6_print_residency()
859 with_intel_runtime_pm(gt->uncore->rpm, wakeref) in intel_rc6_print_residency()
861 intel_uncore_read(gt->uncore, reg), in intel_rc6_print_residency()
862 intel_rc6_residency_us(>->rc6, id)); in intel_rc6_print_residency()