Lines Matching +full:0 +full:x11300
11 #define VLV_GUNIT_BASE 0x180000
25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
26 #define MTL_CAGF_MASK REG_GENMASK(8, 0)
27 #define MTL_CC0 0x0
28 #define MTL_CC6 0x3
32 #define RPM_CONFIG0 _MMIO(0xd00)
35 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
38 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SH…
39 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
44 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_…
46 #define RPM_CONFIG1 _MMIO(0xd04)
50 #define RCP_CONFIG _MMIO(0xd08)
52 #define RC6_LOCATION _MMIO(0xd40)
53 #define RC6_CTX_IN_DRAM (1 << 0)
54 #define RC6_CTX_BASE _MMIO(0xd48)
55 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
57 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
58 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
59 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
60 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
62 #define FORCEWAKE_ACK_GSC _MMIO(0xdf8)
63 #define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
65 #define GMD_ID_GRAPHICS _MMIO(0xd8c)
66 #define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
68 #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
69 #define MTL_STEER_SEMAPHORE _MMIO(0xfd0)
70 #define MTL_MCR_SELECTOR _MMIO(0xfd4)
71 #define SF_MCR_SELECTOR _MMIO(0xfd8)
72 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
73 #define GAM_MCR_SELECTOR _MMIO(0xfe0)
79 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
80 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
81 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
82 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
84 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
86 #define IPEIR_I965 _MMIO(0x2064)
87 #define IPEHR_I965 _MMIO(0x2068)
94 #define INSTPS _MMIO(0x2070) /* 965+ only */
95 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
96 #define ACTHD_I965 _MMIO(0x2074)
97 #define HWS_PGA _MMIO(0x2080)
98 #define HWS_ADDRESS_MASK 0xfffff000
101 #define _3D_CHICKEN _MMIO(0x2084)
104 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
105 #define PWRCTX_EN (1 << 0)
107 #define FF_SLICE_CHICKEN _MMIO(0x2088)
114 #define _3D_CHICKEN2 _MMIO(0x208c)
121 #define _3D_CHICKEN3 _MMIO(0x2090)
129 #define GEN2_INSTDONE _MMIO(0x2090)
130 #define NOPID _MMIO(0x2094)
131 #define HWSTAM _MMIO(0x2098)
133 #define WAIT_FOR_RC6_EXIT _MMIO(0x20cc)
136 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
138 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
140 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
145 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
147 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
150 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIF…
152 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
155 #define GEN6_GT_MODE _MMIO(0x20d0)
157 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
158 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
159 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
164 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
167 #define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
170 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
173 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
178 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
180 #define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20ec)
181 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0)
184 #define GEN8_STATE_ACK _MMIO(0x20f0)
185 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20f8)
186 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
195 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
203 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
205 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
223 #define CXT_SIZE _MMIO(0x21a0)
224 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
225 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
226 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
227 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
228 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
232 #define GEN7_CXT_SIZE _MMIO(0x21a8)
233 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
234 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
235 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
236 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
237 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
238 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
242 #define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214)
244 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
247 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
248 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
250 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
251 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
253 #define HS_INVOCATION_COUNT _MMIO(0x2300)
254 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
255 #define DS_INVOCATION_COUNT _MMIO(0x2308)
256 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
257 #define IA_VERTICES_COUNT _MMIO(0x2310)
258 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
259 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
260 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
261 #define VS_INVOCATION_COUNT _MMIO(0x2320)
262 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
263 #define GS_INVOCATION_COUNT _MMIO(0x2328)
264 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
265 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
266 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
267 #define CL_INVOCATION_COUNT _MMIO(0x2338)
268 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
269 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
270 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
271 #define PS_INVOCATION_COUNT _MMIO(0x2348)
272 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
273 #define PS_DEPTH_COUNT _MMIO(0x2350)
274 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
275 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
276 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
277 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
278 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
279 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243c)
280 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
281 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
282 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
283 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
285 #define GFX_MODE _MMIO(0x2520)
287 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
288 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
290 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
291 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
292 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
295 #define DRAW_WATERMARK _MMIO(0x26c0)
296 #define VERT_WM_VAL REG_GENMASK(9, 0)
298 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
300 #define RENDER_HWS_PGA_GEN7 _MMIO(0x4080)
302 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
303 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
306 #define GAM_ECOCHK _MMIO(0x4090)
311 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
312 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
313 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
314 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
315 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
316 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
317 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
319 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
320 #define _RING_FAULT_REG_RCS 0x4094
321 #define _RING_FAULT_REG_VCS 0x4194
322 #define _RING_FAULT_REG_BCS 0x4294
323 #define _RING_FAULT_REG_VECS 0x4394
330 #define ERROR_GEN6 _MMIO(0x40a0)
332 #define DONE_REG _MMIO(0x40b0)
333 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
334 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
335 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
336 #define BSD_HWS_PGA_GEN7 _MMIO(0x4180)
338 #define GEN12_CCS_AUX_INV _MMIO(0x4208)
339 #define GEN12_VD0_AUX_INV _MMIO(0x4218)
340 #define GEN12_VE0_AUX_INV _MMIO(0x4238)
341 #define GEN12_BCS0_AUX_INV _MMIO(0x4248)
343 #define GEN8_RTCR _MMIO(0x4260)
344 #define GEN8_M1TCR _MMIO(0x4264)
345 #define GEN8_M2TCR _MMIO(0x4268)
346 #define GEN8_BTCR _MMIO(0x426c)
347 #define GEN8_VTCR _MMIO(0x4270)
349 #define BLT_HWS_PGA_GEN7 _MMIO(0x4280)
351 #define GEN12_VD2_AUX_INV _MMIO(0x4298)
352 #define GEN12_CCS0_AUX_INV _MMIO(0x42c8)
353 #define AUX_INV REG_BIT(0)
355 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380)
357 #define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
359 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
361 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
363 0x4800, 0x4804, \
364 0x4848, 0x484c)
368 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
371 #define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
374 #define GAMTARBMODE _MMIO(0x4a08)
378 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
381 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
386 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
387 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
389 #define GEN11_GACB_PERF_CTRL _MMIO(0x4b80)
390 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
391 #define GEN11_HASH_CTRL_BIT0 (1 << 0)
395 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
396 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
397 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
398 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
399 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
401 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
406 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
407 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
409 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
410 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
412 #define GEN9_WM_CHICKEN3 _MMIO(0x5588)
415 #define XEHP_CULLBIT1 MCR_REG(0x6100)
417 #define CHICKEN_RASTER_2 MCR_REG(0x6208)
420 #define VFLSKPD MCR_REG(0x62a8)
423 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
425 #define GEN12_FF_MODE2 _MMIO(0x6604)
426 #define XEHP_FF_MODE2 MCR_REG(0x6604)
432 #define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
434 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
436 #define RC_OP_FLUSH_ENABLE (1 << 0)
438 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
444 #define GEN7_GT_MODE _MMIO(0x7008)
445 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
449 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
453 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
457 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
459 #define HIZ_CHICKEN _MMIO(0x7018)
465 #define XEHP_CULLBIT2 MCR_REG(0x7030)
467 #define GEN8_L3CNTLREG _MMIO(0x7034)
470 #define XEHP_PSS_MODE2 MCR_REG(0x703c)
473 #define XEHP_PSS_CHICKEN MCR_REG(0x7044)
476 #define GEN7_SC_INSTDONE _MMIO(0x7100)
477 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
478 #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
481 #define HDC_CHICKEN0 _MMIO(0x7300)
489 #define COMMON_SLICE_CHICKEN4 _MMIO(0x7300)
492 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
494 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
495 #define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
501 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
502 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
506 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
507 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
508 ((slice) % 3) * 0x4)
509 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
511 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
513 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
514 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
515 ((slice) % 3) * 0x8)
516 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
517 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
518 ((slice) % 3) * 0x8)
519 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
528 #define VF_PREEMPTION _MMIO(0x83a4)
529 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
531 #define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4)
534 #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
536 #define GEN12_SQCNT1 _MMIO(0x8718)
541 #define XEHP_SQCM MCR_REG(0x8724)
544 #define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
545 #define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
547 #define HSW_IDICR _MMIO(0x9008)
548 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
550 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
553 #define GEN6_MBC_SNPCR_MAX (0 << 21)
558 #define VLV_G3DCTL _MMIO(0x9024)
559 #define VLV_GSCKGCTL _MMIO(0x9028)
562 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
565 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
568 #define GEN6_MBCTL _MMIO(0x907c)
573 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
576 #define XEHP_FUSE4 _MMIO(0x9114)
578 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
580 #define GEN10_L3BANK_MASK 0x0F
583 #define GEN12_MEML3_EN_MASK 0x0F
585 #define HSW_PAVP_FUSE1 _MMIO(0x911c)
588 #define HSW_F1_EU_DIS_10EUS 0
592 #define GEN8_FUSE2 _MMIO(0x9120)
594 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
596 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
598 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
600 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
602 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
604 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
605 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
606 #define GEN11_EU_DISABLE _MMIO(0x9134)
607 #define GEN8_EU_DIS0_S0_MASK 0xffffff
609 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
610 #define GEN11_EU_DIS_MASK 0xFF
611 #define XEHP_EU_ENABLE _MMIO(0x9134)
612 #define XEHP_EU_ENA_MASK 0xFF
614 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
615 #define GEN8_EU_DIS1_S1_MASK 0xffff
617 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
619 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
620 #define GEN11_GT_S_ENA_MASK 0xFF
622 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
623 #define GEN8_EU_DIS2_S2_MASK 0xff
625 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c)
626 #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
628 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
629 #define GEN10_EU_DIS_SS_MASK 0xff
630 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
631 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff
633 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
635 #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
636 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
638 #define GEN6_UCGCTL1 _MMIO(0x9400)
644 #define GEN6_UCGCTL2 _MMIO(0x9404)
652 #define GEN6_UCGCTL3 _MMIO(0x9408)
655 #define GEN7_UCGCTL4 _MMIO(0x940c)
659 #define GEN6_RCGCTL1 _MMIO(0x9410)
660 #define GEN6_RCGCTL2 _MMIO(0x9414)
662 #define GEN6_GDRST _MMIO(0x941c)
663 #define GEN6_GRDOM_FULL (1 << 0)
703 #define GEN6_RSTCTL _MMIO(0x9420)
705 #define GEN7_MISCCPCTL _MMIO(0x9424)
706 #define GEN7_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
712 #define GEN8_UCGCTL6 _MMIO(0x9430)
717 #define UNSLCGCTL9430 _MMIO(0x9430)
720 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
727 #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
728 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
736 #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
740 #define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
744 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
747 #define SSMCGCTL9530 MCR_REG(0x9530)
750 #define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
753 #define MICRO_BP0_0 _MMIO(0x9800)
754 #define MICRO_BP0_2 _MMIO(0x9804)
755 #define MICRO_BP0_1 _MMIO(0x9808)
756 #define MICRO_BP1_0 _MMIO(0x980c)
757 #define MICRO_BP1_2 _MMIO(0x9810)
758 #define MICRO_BP1_1 _MMIO(0x9814)
759 #define MICRO_BP2_0 _MMIO(0x9818)
760 #define MICRO_BP2_2 _MMIO(0x981c)
761 #define MICRO_BP2_1 _MMIO(0x9820)
762 #define MICRO_BP3_0 _MMIO(0x9824)
763 #define MICRO_BP3_2 _MMIO(0x9828)
764 #define MICRO_BP3_1 _MMIO(0x982c)
765 #define MICRO_BP_TRIGGER _MMIO(0x9830)
766 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
767 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
768 #define MICRO_BP_FIRED_ARMED _MMIO(0x983c)
770 #define GEN6_GFXPAUSE _MMIO(0xa000)
771 #define GEN6_RPNSWREQ _MMIO(0xa008)
777 #define GEN6_AGGRESSIVE_TURBO (0 << 15)
779 #define GEN9_IGNORE_SLICE_RATIO (0 << 0)
782 #define GEN6_RC_VIDEO_FREQ _MMIO(0xa00c)
792 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
793 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
794 #define GEN6_RPSTAT1 _MMIO(0xa01c)
798 #define GEN6_RP_CONTROL _MMIO(0xa024)
804 #define GEN6_RP_MEDIA_SW_MODE (0 << 9)
807 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
808 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
809 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
810 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
811 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
813 #define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT)
814 #define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT)
815 #define GEN6_RP_UP_THRESHOLD _MMIO(0xa02c)
816 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xa030)
817 #define GEN6_RP_CUR_UP_EI _MMIO(0xa050)
818 #define GEN6_RP_EI_MASK 0xffffff
820 #define GEN6_RP_CUR_UP _MMIO(0xa054)
822 #define GEN6_RP_PREV_UP _MMIO(0xa058)
823 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xa05c)
825 #define GEN6_RP_CUR_DOWN _MMIO(0xa060)
826 #define GEN6_RP_PREV_DOWN _MMIO(0xa064)
827 #define GEN6_RP_UP_EI _MMIO(0xa068)
828 #define GEN6_RP_DOWN_EI _MMIO(0xa06c)
829 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xa070)
830 #define GEN6_RPDEUHWTC _MMIO(0xa080)
831 #define GEN6_RPDEUC _MMIO(0xa084)
832 #define GEN6_RPDEUCSW _MMIO(0xa088)
833 #define GEN6_RC_CONTROL _MMIO(0xa090)
834 #define GEN6_RC_STATE _MMIO(0xa094)
837 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xa098)
838 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xa09c)
839 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xa0a0)
840 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xa0a0)
841 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xa0a8)
842 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xa0ac)
843 #define GEN6_RC_SLEEP _MMIO(0xa0b0)
844 #define GEN6_RCUBMABDTMR _MMIO(0xa0b0)
845 #define GEN6_RC1e_THRESHOLD _MMIO(0xa0b4)
846 #define GEN6_RC6_THRESHOLD _MMIO(0xa0b8)
847 #define GEN6_RC6p_THRESHOLD _MMIO(0xa0bc)
848 #define VLV_RCEDATA _MMIO(0xa0bc)
849 #define GEN6_RC6pp_THRESHOLD _MMIO(0xa0c0)
850 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xa0c4)
851 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xa0c8)
853 #define GEN6_PMINTRMSK _MMIO(0xa168)
857 #define GEN8_MISC_CTRL0 _MMIO(0xa180)
859 #define ECOBUS _MMIO(0xa180)
862 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
863 #define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
864 #define FORCEWAKE _MMIO(0xa18c)
866 #define VLV_SPAREG2H _MMIO(0xa194)
868 #define GEN9_PG_ENABLE _MMIO(0xa210)
869 #define GEN9_RENDER_PG_ENABLE REG_BIT(0)
875 #define GEN8_PUSHBUS_CONTROL _MMIO(0xa248)
876 #define GEN8_PUSHBUS_ENABLE _MMIO(0xa250)
877 #define GEN8_PUSHBUS_SHIFT _MMIO(0xa25c)
880 #define CTC_MODE _MMIO(0xa26c)
882 #define CTC_SOURCE_CRYSTAL_CLOCK 0
885 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
888 #define MSG_IDLE_CS _MMIO(0x8000)
889 #define MSG_IDLE_VCS0 _MMIO(0x8004)
890 #define MSG_IDLE_VCS1 _MMIO(0x8008)
891 #define MSG_IDLE_BCS _MMIO(0x800C)
892 #define MSG_IDLE_VECS0 _MMIO(0x8010)
893 #define MSG_IDLE_VCS2 _MMIO(0x80C0)
894 #define MSG_IDLE_VCS3 _MMIO(0x80C4)
895 #define MSG_IDLE_VCS4 _MMIO(0x80C8)
896 #define MSG_IDLE_VCS5 _MMIO(0x80CC)
897 #define MSG_IDLE_VCS6 _MMIO(0x80D0)
898 #define MSG_IDLE_VCS7 _MMIO(0x80D4)
899 #define MSG_IDLE_VECS1 _MMIO(0x80D8)
900 #define MSG_IDLE_VECS2 _MMIO(0x80DC)
901 #define MSG_IDLE_VECS3 _MMIO(0x80E0)
905 #define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050)
906 #define IDLE_MSG_DISABLE REG_BIT(0)
907 #define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054)
909 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
910 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
912 #define VLV_PWRDWNUPCTL _MMIO(0xa294)
914 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xa2a0)
915 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
918 #define MISC_STATUS0 _MMIO(0xa500)
919 #define MISC_STATUS1 _MMIO(0xa504)
921 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
922 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
924 #define FORCEWAKE_REQ_GSC _MMIO(0xa618)
926 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
927 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
928 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
933 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
936 #define GEN7_SARCHKMD _MMIO(0xb000)
940 #define GEN8_GARBCNTL _MMIO(0xb004)
944 #define GEN11_HASH_CTRL_EXCL_MASK REG_GENMASK(6, 0)
945 #define GEN11_HASH_CTRL_EXCL_BIT0 REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1)
947 #define GEN9_SCRATCH_LNCF1 _MMIO(0xb008)
948 #define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
950 #define GEN7_L3SQCREG1 _MMIO(0xb010)
951 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
953 #define GEN7_L3CNTLREG1 _MMIO(0xb01c)
954 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
957 #define GEN7_L3CNTLREG2 _MMIO(0xb020)
960 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
961 #define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4)
964 #define GEN7_L3CNTLREG3 _MMIO(0xb024)
966 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xb030)
967 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
969 #define GEN7_L3SQCREG4 _MMIO(0xb034)
972 #define HSW_SCRATCH1 _MMIO(0xb038)
975 #define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
976 #define GEN7_L3LOG_SIZE 0x80
978 #define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
981 #define GEN8_L3SQCREG1 MCR_REG(0xb100)
990 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
992 #define GEN8_L3SQCREG4 MCR_REG(0xb118)
998 #define GEN9_SCRATCH1 MCR_REG(0xb11c)
1001 #define BDW_SCRATCH1 MCR_REG(0xb11c)
1004 #define GEN11_SCRATCH2 MCR_REG(0xb140)
1007 #define XEHP_L3SQCREG5 MCR_REG(0xb158)
1008 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
1010 #define XEHP_L3SCQREG7 MCR_REG(0xb188)
1013 #define GEN11_GLBLINVL _MMIO(0xb404)
1014 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
1017 #define GEN11_LSN_UNSLCVC _MMIO(0xb43c)
1021 #define GUCPMTIMESTAMP _MMIO(0xc3e8)
1023 #define __GEN9_RCS0_MOCS0 0xc800
1025 #define __GEN9_VCS0_MOCS0 0xc900
1027 #define __GEN9_VCS1_MOCS0 0xca00
1029 #define __GEN9_VECS0_MOCS0 0xcb00
1031 #define __GEN9_BCS0_MOCS0 0xcc00
1034 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
1035 #define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
1036 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
1037 #define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
1038 #define FAULT_VA_HIGH_BITS (0xf << 0)
1041 #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
1042 #define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
1043 #define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
1044 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
1046 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
1047 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
1048 #define RING_FAULT_VALID (1 << 0)
1050 #define GEN12_GFX_TLB_INV_CR _MMIO(0xced8)
1051 #define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8)
1052 #define GEN12_VD_TLB_INV_CR _MMIO(0xcedc)
1053 #define XEHP_VD_TLB_INV_CR MCR_REG(0xcedc)
1054 #define GEN12_VE_TLB_INV_CR _MMIO(0xcee0)
1055 #define XEHP_VE_TLB_INV_CR MCR_REG(0xcee0)
1056 #define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
1057 #define XEHP_BLT_TLB_INV_CR MCR_REG(0xcee4)
1058 #define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
1059 #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
1060 #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
1062 #define RENDER_MOD_CTRL MCR_REG(0xcf2c)
1063 #define COMP_MOD_CTRL MCR_REG(0xcf30)
1064 #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
1065 #define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34)
1066 #define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34)
1067 #define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38)
1068 #define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38)
1071 #define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
1076 #define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
1080 #define GEN12_GAM_DONE _MMIO(0xcf68)
1082 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
1083 #define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100)
1089 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1090 #define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160)
1091 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
1092 #define GEN8_ROW_INSTDONE MCR_REG(0xe164)
1094 #define HALF_SLICE_CHICKEN2 MCR_REG(0xe180)
1097 #define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
1098 #define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184)
1104 #define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188)
1108 #define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
1113 #define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0)
1115 #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
1121 #define GEN10_CACHE_MODE_SS MCR_REG(0xe420)
1133 #define EU_PERF_CNTL0 PERF_REG(0xe458)
1134 #define EU_PERF_CNTL4 PERF_REG(0xe45c)
1136 #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
1142 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
1144 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
1145 #define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c)
1149 #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
1158 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
1160 #define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
1166 #define GEN12_DISABLE_DOP_GATING REG_BIT(0)
1168 #define RT_CTRL MCR_REG(0xe530)
1171 #define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
1173 #define EU_PERF_CNTL1 PERF_REG(0xe558)
1174 #define EU_PERF_CNTL5 PERF_REG(0xe55c)
1176 #define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
1180 #define ICL_HDC_MODE MCR_REG(0xe5f4)
1182 #define EU_PERF_CNTL2 PERF_REG(0xe658)
1183 #define EU_PERF_CNTL6 PERF_REG(0xe65c)
1184 #define EU_PERF_CNTL3 PERF_REG(0xe758)
1186 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
1189 #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
1197 #define SARB_CHICKEN1 MCR_REG(0xe90c)
1200 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
1201 #define DOP_CLOCK_GATING_DISABLE (1 << 0)
1205 #define __GEN11_VCS2_MOCS0 0x10000
1208 #define CRSTANDVID _MMIO(0x11100)
1209 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1210 #define PXVFREQ_PX_MASK 0x7f000000
1212 #define VIDFREQ_BASE _MMIO(0x11110)
1213 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1214 #define VIDFREQ2 _MMIO(0x11114)
1215 #define VIDFREQ3 _MMIO(0x11118)
1216 #define VIDFREQ4 _MMIO(0x1111c)
1217 #define VIDFREQ_P0_MASK 0x1f000000
1219 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1221 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1223 #define VIDFREQ_P1_MASK 0x00001f00
1225 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1227 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1228 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
1230 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1232 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1234 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1235 #define INTTOEXT_MAP0_SHIFT 0
1236 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1237 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
1238 #define MEMCTL_CMD_MASK 0xe000
1240 #define MEMCTL_CMD_RCLK_OFF 0
1248 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1251 #define MEMCTL_TGT_VID_MASK 0x007f
1252 #define MEMIHYST _MMIO(0x1117c)
1253 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
1262 #define MEMINT_SW_CMD_EN (1 << 0)
1263 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
1264 #define MEM_RSEXIT_MASK 0xc000
1266 #define MEM_CONT_BUSY_MASK 0x3000
1268 #define MEM_AVG_BUSY_MASK 0x0c00
1270 #define MEM_EVAL_CHG_MASK 0x0300
1272 #define MEM_MON_IDLE_MASK 0x00c0
1274 #define MEM_UP_EVAL_MASK 0x0030
1276 #define MEM_DOWN_EVAL_MASK 0x000c
1278 #define MEM_SW_CMD_MASK 0x0003
1279 #define MEM_INT_STEER_GFX 0
1283 #define MEMINTRSTS _MMIO(0x11184)
1291 #define MEMINT_SW_CMD (1 << 0)
1292 #define MEMMODECTL _MMIO(0x11190)
1294 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1296 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1298 #define MEMMODE_IDLE_MODE_EVAL 0
1304 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1306 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1308 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1309 #define RCBMAXAVG _MMIO(0x1119c)
1310 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
1311 #define SWMEMCMD_RENDER_OFF (0 << 13)
1319 #define SWFREQ_MASK 0x0380 /* P0-7 */
1321 #define TARVID_MASK 0x001f
1322 #define MEMSTAT_CTG _MMIO(0x111a0)
1323 #define RCBMINAVG _MMIO(0x111a0)
1324 #define RCUPEI _MMIO(0x111b0)
1325 #define RCDNEI _MMIO(0x111b4)
1326 #define RSTDBYCTL _MMIO(0x111b8)
1337 #define RSX_STATUS_ON (0 << 20)
1350 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
1355 #define SLOW_RS123 (0 << 12)
1359 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
1362 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
1364 #define RS_CSTATE_C367_RS1 (0 << 4)
1370 #define VIDCTL _MMIO(0x111c0)
1371 #define VIDSTS _MMIO(0x111c8)
1372 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
1373 #define MEMSTAT_ILK _MMIO(0x111f8)
1374 #define MEMSTAT_VID_MASK 0x7f00
1378 #define MEMSTAT_SRC_CTL_MASK 0x0003
1379 #define MEMSTAT_SRC_CTL_CORE 0
1383 #define PMMISC _MMIO(0x11214)
1384 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
1385 #define SDEW _MMIO(0x1124c)
1386 #define CSIEW0 _MMIO(0x11250)
1387 #define CSIEW1 _MMIO(0x11254)
1388 #define CSIEW2 _MMIO(0x11258)
1389 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
1390 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
1391 #define MCHAFE _MMIO(0x112c0)
1392 #define CSIEC _MMIO(0x112e0)
1393 #define DMIEC _MMIO(0x112e4)
1394 #define DDREC _MMIO(0x112e8)
1395 #define PEG0EC _MMIO(0x112ec)
1396 #define PEG1EC _MMIO(0x112f0)
1397 #define GFXEC _MMIO(0x112f4)
1398 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
1399 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
1400 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
1401 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
1402 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
1403 #define ECR _MMIO(0x11600)
1406 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1407 #define OGW0 _MMIO(0x11608)
1408 #define OGW1 _MMIO(0x1160c)
1409 #define EG0 _MMIO(0x11610)
1410 #define EG1 _MMIO(0x11614)
1411 #define EG2 _MMIO(0x11618)
1412 #define EG3 _MMIO(0x1161c)
1413 #define EG4 _MMIO(0x11620)
1414 #define EG5 _MMIO(0x11624)
1415 #define EG6 _MMIO(0x11628)
1416 #define EG7 _MMIO(0x1162c)
1417 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
1418 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
1419 #define LCFUSE02 _MMIO(0x116c0)
1420 #define LCFUSE_HIV_MASK 0x000000ff
1422 #define GAC_ECO_BITS _MMIO(0x14090)
1425 #define ECOBITS_PPGTT_CACHE4B (0 << 8)
1427 #define GEN12_RCU_MODE _MMIO(0x14800)
1429 #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
1431 #define XEHP_CCS_MODE _MMIO(0x14804)
1432 #define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 + rsvd */
1436 #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
1440 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1442 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1444 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1446 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1448 #define BCS_SWCTRL _MMIO(0x22200)
1449 #define BCS_SRC_Y REG_BIT(0)
1452 #define GAB_CTL _MMIO(0x24000)
1455 #define GEN6_PMISR _MMIO(0x44020)
1456 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
1457 #define GEN6_PMIIR _MMIO(0x44028)
1458 #define GEN6_PMIER _MMIO(0x4402c)
1480 #define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4)
1483 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
1484 #define GFX_FLSH_CNTL_EN (1 << 0)
1486 #define GTFIFODBG _MMIO(0x120000)
1487 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
1488 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
1495 #define GT_FIFO_IARDERR (1 << 0)
1497 #define GTFIFOCTL _MMIO(0x120008)
1498 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
1503 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
1504 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
1505 #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
1506 #define FORCEWAKE_KERNEL BIT(0)
1509 #define FORCEWAKE_ACK _MMIO(0x130090)
1510 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
1513 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
1514 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
1515 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
1519 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
1522 #define FORCEWAKE_VLV _MMIO(0x1300b0)
1523 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
1524 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
1525 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
1527 #define MTL_MEDIA_MC6 _MMIO(0x138048)
1529 #define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
1532 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
1533 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1535 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
1538 #define GEN6_RC0 0
1543 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
1544 #define GEN8_LSLICESTAT_MASK 0x7
1546 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
1547 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
1552 #define VLV_RENDER_RC6_COUNT_EN (1 << 0)
1553 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
1554 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810c)
1556 #define GEN6_GT_GFX_RC6p _MMIO(0x13810c)
1557 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
1558 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
1559 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
1561 #define PCU_PWM_FAN_SPEED _MMIO(0x138140)
1563 #define GEN12_RPSTAT1 _MMIO(0x1381b4)
1564 #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
1567 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
1589 #define GEN11_RCS0 (0)
1593 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
1594 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
1595 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
1597 #define ENGINE0_MASK REG_GENMASK(15, 0)
1598 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
1599 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
1600 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
1601 #define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
1603 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
1607 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
1609 #define OTHER_GUC_INSTANCE 0
1617 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
1619 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
1620 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
1621 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
1622 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
1623 #define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
1624 #define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
1625 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
1626 #define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
1627 #define GEN12_HECI2_RSVD_INTR_MASK _MMIO(0x1900e4)
1628 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
1629 #define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */
1630 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
1631 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
1632 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
1633 #define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
1634 #define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
1635 #define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
1636 #define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
1637 #define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
1638 #define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
1640 #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
1644 * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
1648 #define MTL_MEDIA_GSI_BASE 0x380000