89 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in vlv_dsi_wait_for_fifo_empty()  local
95 	if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),  in vlv_dsi_wait_for_fifo_empty()
97 		drm_err(display->drm, "DPI FIFOs are not empty\n");  in vlv_dsi_wait_for_fifo_empty()
100 static void write_data(struct intel_display *display,  in write_data()  argument
112 		intel_de_write(display, reg, val);  in write_data()
116 static void read_data(struct intel_display *display,  in read_data()  argument
123 		u32 val = intel_de_read(display, reg);  in read_data()
135 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in intel_dsi_host_transfer()  local
150 		data_reg = MIPI_LP_GEN_DATA(display, port);  in intel_dsi_host_transfer()
152 		ctrl_reg = MIPI_LP_GEN_CTRL(display, port);  in intel_dsi_host_transfer()
155 		data_reg = MIPI_HS_GEN_DATA(display, port);  in intel_dsi_host_transfer()
157 		ctrl_reg = MIPI_HS_GEN_CTRL(display, port);  in intel_dsi_host_transfer()
163 		if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),  in intel_dsi_host_transfer()
165 			drm_err(display->drm,  in intel_dsi_host_transfer()
168 		write_data(display, data_reg, packet.payload,  in intel_dsi_host_transfer()
173 		intel_de_write(display, MIPI_INTR_STAT(display, port),  in intel_dsi_host_transfer()
177 	if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port),  in intel_dsi_host_transfer()
179 		drm_err(display->drm,  in intel_dsi_host_transfer()
183 	intel_de_write(display, ctrl_reg,  in intel_dsi_host_transfer()
189 		if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port),  in intel_dsi_host_transfer()
191 			drm_err(display->drm,  in intel_dsi_host_transfer()
194 		read_data(display, data_reg, msg->rx_buf, msg->rx_len);  in intel_dsi_host_transfer()
227 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in dpi_send_cmd()  local
237 	intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT);  in dpi_send_cmd()
240 	if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))  in dpi_send_cmd()
241 		drm_dbg_kms(display->drm,  in dpi_send_cmd()
244 	intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd);  in dpi_send_cmd()
247 	if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100))  in dpi_send_cmd()
248 		drm_err(display->drm,  in dpi_send_cmd()
328 	struct intel_display *display = to_intel_display(encoder);  in glk_dsi_enable_io()  local
338 		intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE);  in glk_dsi_enable_io()
341 	intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);  in glk_dsi_enable_io()
345 		u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));  in glk_dsi_enable_io()
347 		intel_de_rmw(display, MIPI_CTRL(display, port),  in glk_dsi_enable_io()
353 		if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),  in glk_dsi_enable_io()
355 			drm_err(display->drm, "MIPIO port is powergated\n");  in glk_dsi_enable_io()
361 			!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);  in glk_dsi_enable_io()
369 	struct intel_display *display = to_intel_display(encoder);  in glk_dsi_device_ready()  local
375 		if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),  in glk_dsi_device_ready()
377 			drm_err(display->drm, "PHY is not ON\n");  in glk_dsi_device_ready()
381 	intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);  in glk_dsi_device_ready()
385 		if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {  in glk_dsi_device_ready()
386 			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),  in glk_dsi_device_ready()
391 			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),  in glk_dsi_device_ready()
395 			if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),  in glk_dsi_device_ready()
397 				drm_err(display->drm, "ULPS not active\n");  in glk_dsi_device_ready()
400 			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),  in glk_dsi_device_ready()
404 			intel_de_rmw(display, MIPI_DEVICE_READY(display, port),  in glk_dsi_device_ready()
408 			intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0);  in glk_dsi_device_ready()
414 		if (intel_de_wait_for_set(display, MIPI_CTRL(display, port),  in glk_dsi_device_ready()
416 			drm_err(display->drm,  in glk_dsi_device_ready()
422 		if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port),  in glk_dsi_device_ready()
424 			drm_err(display->drm,  in glk_dsi_device_ready()
431 	struct intel_display *display = to_intel_display(encoder);  in bxt_dsi_device_ready()  local
436 	drm_dbg_kms(display->drm, "\n");  in bxt_dsi_device_ready()
440 		intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);  in bxt_dsi_device_ready()
446 		val = intel_de_read(display, MIPI_DEVICE_READY(display, port));  in bxt_dsi_device_ready()
448 		intel_de_write(display, MIPI_DEVICE_READY(display, port), val);  in bxt_dsi_device_ready()
451 		intel_de_write(display, MIPI_DEVICE_READY(display, port), val);  in bxt_dsi_device_ready()
457 	struct intel_display *display = to_intel_display(encoder);  in vlv_dsi_device_ready()  local
462 	drm_dbg_kms(display->drm, "\n");  in vlv_dsi_device_ready()
475 		intel_de_write(display, MIPI_DEVICE_READY(display, port),  in vlv_dsi_device_ready()
483 		intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);  in vlv_dsi_device_ready()
486 		intel_de_write(display, MIPI_DEVICE_READY(display, port),  in vlv_dsi_device_ready()
490 		intel_de_write(display, MIPI_DEVICE_READY(display, port),  in vlv_dsi_device_ready()
510 	struct intel_display *display = to_intel_display(encoder);  in glk_dsi_enter_low_power_mode()  local
516 		intel_de_rmw(display, MIPI_DEVICE_READY(display, port),  in glk_dsi_enter_low_power_mode()
521 		if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),  in glk_dsi_enter_low_power_mode()
523 			drm_err(display->drm, "PHY is not turning OFF\n");  in glk_dsi_enter_low_power_mode()
528 		if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),  in glk_dsi_enter_low_power_mode()
530 			drm_err(display->drm,  in glk_dsi_enter_low_power_mode()
537 	struct intel_display *display = to_intel_display(encoder);  in glk_dsi_disable_mipi_io()  local
542 	intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);  in glk_dsi_disable_mipi_io()
546 		if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port),  in glk_dsi_disable_mipi_io()
548 			drm_err(display->drm, "PHY is not turning OFF\n");  in glk_dsi_disable_mipi_io()
553 		intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0);  in glk_dsi_disable_mipi_io()
570 	struct intel_display *display = to_intel_display(encoder);  in vlv_dsi_clear_device_ready()  local
575 	drm_dbg_kms(display->drm, "\n");  in vlv_dsi_clear_device_ready()
581 		intel_de_write(display, MIPI_DEVICE_READY(display, port),  in vlv_dsi_clear_device_ready()
585 		intel_de_write(display, MIPI_DEVICE_READY(display, port),  in vlv_dsi_clear_device_ready()
589 		intel_de_write(display, MIPI_DEVICE_READY(display, port),  in vlv_dsi_clear_device_ready()
598 		    intel_de_wait_for_clear(display, port_ctrl,  in vlv_dsi_clear_device_ready()
600 			drm_err(display->drm, "DSI LP not going Low\n");  in vlv_dsi_clear_device_ready()
603 		intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0);  in vlv_dsi_clear_device_ready()
606 		intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00);  in vlv_dsi_clear_device_ready()
614 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_port_enable()  local
625 				intel_de_rmw(display, MIPI_CTRL(display, port),  in intel_dsi_port_enable()
629 			intel_de_rmw(display, VLV_CHICKEN_3,  in intel_dsi_port_enable()
639 		temp = intel_de_read(display, port_ctrl);  in intel_dsi_port_enable()
659 		intel_de_write(display, port_ctrl, temp | DPI_ENABLE);  in intel_dsi_port_enable()
660 		intel_de_posting_read(display, port_ctrl);  in intel_dsi_port_enable()
666 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_port_disable()  local
675 		intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);  in intel_dsi_port_disable()
676 		intel_de_posting_read(display, port_ctrl);  in intel_dsi_port_disable()
730 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_pre_enable()  local
738 	drm_dbg_kms(display->drm, "\n");  in intel_dsi_pre_enable()
758 		intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);  in intel_dsi_pre_enable()
761 		intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);  in intel_dsi_pre_enable()
762 		intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0);  in intel_dsi_pre_enable()
767 		intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),  in intel_dsi_pre_enable()
803 			intel_de_write(display,  in intel_dsi_pre_enable()
804 				       MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4);  in intel_dsi_pre_enable()
876 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_post_disable()  local
881 	drm_dbg_kms(display->drm, "\n");  in intel_dsi_post_disable()
912 		intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);  in intel_dsi_post_disable()
913 		intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL,  in intel_dsi_post_disable()
917 		intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);  in intel_dsi_post_disable()
925 		intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),  in intel_dsi_post_disable()
941 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_get_hw_state()  local
948 	drm_dbg_kms(display->drm, "\n");  in intel_dsi_get_hw_state()
958 	 * machine. See BSpec North Display Engine registers/MIPI[BXT].  in intel_dsi_get_hw_state()
967 		bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;  in intel_dsi_get_hw_state()
976 			enabled = intel_de_read(display,  in intel_dsi_get_hw_state()
981 			u32 tmp = intel_de_read(display,  in intel_dsi_get_hw_state()
982 						MIPI_DSI_FUNC_PRG(display, port));  in intel_dsi_get_hw_state()
989 		if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))  in intel_dsi_get_hw_state()
993 			u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));  in intel_dsi_get_hw_state()
997 			if (drm_WARN_ON(display->drm, tmp > PIPE_C))  in intel_dsi_get_hw_state()
1018 	struct intel_display *display = to_intel_display(encoder);  in bxt_dsi_get_pipe_config()  local
1040 		if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)  in bxt_dsi_get_pipe_config()
1044 	fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;  in bxt_dsi_get_pipe_config()
1056 				intel_de_read(display,  in bxt_dsi_get_pipe_config()
1059 				intel_de_read(display,  in bxt_dsi_get_pipe_config()
1062 				intel_de_read(display,  in bxt_dsi_get_pipe_config()
1066 	hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));  in bxt_dsi_get_pipe_config()
1072 	hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));  in bxt_dsi_get_pipe_config()
1073 	hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));  in bxt_dsi_get_pipe_config()
1090 	vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));  in bxt_dsi_get_pipe_config()
1091 	vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));  in bxt_dsi_get_pipe_config()
1220 	struct intel_display *display = to_intel_display(encoder);  in set_dsi_timings()  local
1263 			intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port),  in set_dsi_timings()
1265 			intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),  in set_dsi_timings()
1267 			intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),  in set_dsi_timings()
1271 		intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),  in set_dsi_timings()
1273 		intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp);  in set_dsi_timings()
1277 		intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port),  in set_dsi_timings()
1279 		intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp);  in set_dsi_timings()
1282 		intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp);  in set_dsi_timings()
1283 		intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port),  in set_dsi_timings()
1285 		intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp);  in set_dsi_timings()
1309 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_prepare()  local
1319 	drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe));  in intel_dsi_prepare()
1335 			tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));  in intel_dsi_prepare()
1337 			intel_de_write(display, MIPI_CTRL(display, PORT_A),  in intel_dsi_prepare()
1341 			tmp = intel_de_read(display, MIPI_CTRL(display, port));  in intel_dsi_prepare()
1343 			intel_de_write(display, MIPI_CTRL(display, port),  in intel_dsi_prepare()
1348 			intel_de_rmw(display, MIPI_CTRL(display, port),  in intel_dsi_prepare()
1353 		intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff);  in intel_dsi_prepare()
1354 		intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff);  in intel_dsi_prepare()
1356 		intel_de_write(display, MIPI_DPHY_PARAM(display, port),  in intel_dsi_prepare()
1359 		intel_de_write(display, MIPI_DPI_RESOLUTION(display, port),  in intel_dsi_prepare()
1387 		intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val);  in intel_dsi_prepare()
1408 			intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),  in intel_dsi_prepare()
1411 			intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port),  in intel_dsi_prepare()
1414 		intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port),  in intel_dsi_prepare()
1416 		intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port),  in intel_dsi_prepare()
1418 		intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port),  in intel_dsi_prepare()
1424 		intel_de_write(display, MIPI_INIT_COUNT(display, port),  in intel_dsi_prepare()
1435 			intel_de_write(display,  in intel_dsi_prepare()
1436 				       MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A),  in intel_dsi_prepare()
1441 		intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp);  in intel_dsi_prepare()
1444 		intel_de_write(display, MIPI_INIT_COUNT(display, port),  in intel_dsi_prepare()
1452 		intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port),  in intel_dsi_prepare()
1461 		intel_de_write(display, MIPI_LP_BYTECLK(display, port),  in intel_dsi_prepare()
1465 			intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port),  in intel_dsi_prepare()
1468 			intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port),  in intel_dsi_prepare()
1477 		intel_de_write(display, MIPI_DBI_BW_CTRL(display, port),  in intel_dsi_prepare()
1480 		intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port),  in intel_dsi_prepare()
1508 			intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt);  in intel_dsi_prepare()
1515 	struct intel_display *display = to_intel_display(encoder);  in intel_dsi_unprepare()  local
1525 		intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0);  in intel_dsi_unprepare()
1531 		intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);  in intel_dsi_unprepare()
1533 		intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0);  in intel_dsi_unprepare()
1535 		intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1);  in intel_dsi_unprepare()
1790  * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1908 	struct intel_display *display = &dev_priv->display;  in vlv_dsi_init()  local
1920 	if (!intel_bios_is_dsi_present(display, &port))  in vlv_dsi_init()
1924 		dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;  in vlv_dsi_init()
1926 		dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;  in vlv_dsi_init()
1975 	intel_bios_init_panel_late(display, &connector->panel, NULL, NULL);  in vlv_dsi_init()