372 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
394 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
417 			&crtc_state->wm.skl.optimal.planes[plane_id];  in tgl_crtc_can_enable_sagv()
463 		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;  in intel_compute_sagv_mask()
485 		 * other crtcs can't be allowed to use the more optimal  in intel_compute_sagv_mask()
1591 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1642 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1678 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1708 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
2316 		const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];  in skl_max_wm0_lines()
2377 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_wm_check_vblank()
2396 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_wm_check_vblank()
2433 	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;  in skl_build_pipe_wm()
2689 		old_pipe_wm = &old_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
2690 		new_pipe_wm = &new_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
2883 						 &old_crtc_state->wm.skl.optimal,  in skl_wm_add_affected_planes()
2884 						 &new_crtc_state->wm.skl.optimal))  in skl_wm_add_affected_planes()
3086 		memset(&crtc_state->wm.skl.optimal, 0,  in skl_wm_get_hw_state()
3087 		       sizeof(crtc_state->wm.skl.optimal));  in skl_wm_get_hw_state()
3089 			skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);  in skl_wm_get_hw_state()
3090 		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;  in skl_wm_get_hw_state()
3779 	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;  in intel_wm_state_verify()