Lines Matching +full:no +full:- +full:wp
1 // SPDX-License-Identifier: MIT
80 struct intel_display *display = &i915->display; in intel_has_sagv()
82 return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED; in intel_has_sagv()
88 struct intel_display *display = &i915->display; in intel_sagv_block_time()
100 ret = snb_pcode_read(&i915->uncore, in intel_sagv_block_time()
104 drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n"); in intel_sagv_block_time()
120 struct intel_display *display = &i915->display; in intel_sagv_init()
123 display->sagv.status = I915_SAGV_NOT_CONTROLLED; in intel_sagv_init()
132 drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN); in intel_sagv_init()
134 display->sagv.block_time_us = intel_sagv_block_time(i915); in intel_sagv_init()
136 drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n", in intel_sagv_init()
137 str_yes_no(intel_has_sagv(i915)), display->sagv.block_time_us); in intel_sagv_init()
140 if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX, in intel_sagv_init()
142 display->sagv.block_time_us)) in intel_sagv_init()
143 display->sagv.block_time_us = 0; in intel_sagv_init()
146 display->sagv.block_time_us = 0; in intel_sagv_init()
156 * - <= 1 pipe enabled
157 * - All planes can enable watermarks for latencies >= SAGV engine block time
158 * - We're not using an interlaced display configuration
167 if (i915->display.sagv.status == I915_SAGV_ENABLED) in skl_sagv_enable()
170 drm_dbg_kms(&i915->drm, "Enabling SAGV\n"); in skl_sagv_enable()
171 ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, in skl_sagv_enable()
177 * Some skl systems, pre-release machines in particular, in skl_sagv_enable()
180 if (IS_SKYLAKE(i915) && ret == -ENXIO) { in skl_sagv_enable()
181 drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n"); in skl_sagv_enable()
182 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in skl_sagv_enable()
185 drm_err(&i915->drm, "Failed to enable SAGV\n"); in skl_sagv_enable()
189 i915->display.sagv.status = I915_SAGV_ENABLED; in skl_sagv_enable()
199 if (i915->display.sagv.status == I915_SAGV_DISABLED) in skl_sagv_disable()
202 drm_dbg_kms(&i915->drm, "Disabling SAGV\n"); in skl_sagv_disable()
204 ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL, in skl_sagv_disable()
209 * Some skl systems, pre-release machines in particular, in skl_sagv_disable()
212 if (IS_SKYLAKE(i915) && ret == -ENXIO) { in skl_sagv_disable()
213 drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n"); in skl_sagv_disable()
214 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in skl_sagv_disable()
217 drm_err(&i915->drm, "Failed to disable SAGV (%d)\n", ret); in skl_sagv_disable()
221 i915->display.sagv.status = I915_SAGV_DISABLED; in skl_sagv_disable()
226 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_sagv_pre_plane_update()
239 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_sagv_post_plane_update()
252 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_sagv_pre_plane_update()
262 old_mask = old_bw_state->qgv_points_mask; in icl_sagv_pre_plane_update()
263 new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; in icl_sagv_pre_plane_update()
268 WARN_ON(!new_bw_state->base.changed); in icl_sagv_pre_plane_update()
270 drm_dbg_kms(&i915->drm, "Restricting QGV points: 0x%x -> 0x%x\n", in icl_sagv_pre_plane_update()
284 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_sagv_post_plane_update()
294 old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; in icl_sagv_post_plane_update()
295 new_mask = new_bw_state->qgv_points_mask; in icl_sagv_post_plane_update()
300 WARN_ON(!new_bw_state->base.changed); in icl_sagv_post_plane_update()
302 drm_dbg_kms(&i915->drm, "Relaxing QGV points: 0x%x -> 0x%x\n", in icl_sagv_post_plane_update()
316 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_sagv_pre_plane_update()
321 * afford it due to DBuf limitation - in case if SAGV is completely in intel_sagv_pre_plane_update()
336 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_sagv_post_plane_update()
341 * afford it due to DBuf limitation - in case if SAGV is completely in intel_sagv_post_plane_update()
356 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_crtc_can_enable_sagv()
357 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_crtc_can_enable_sagv()
364 if (!crtc_state->hw.active) in skl_crtc_can_enable_sagv()
367 if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE) in skl_crtc_can_enable_sagv()
372 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
376 if (!wm->wm[0].enable) in skl_crtc_can_enable_sagv()
380 for (level = i915->display.wm.num_levels - 1; in skl_crtc_can_enable_sagv()
381 !wm->wm[level].enable; --level) in skl_crtc_can_enable_sagv()
388 /* No enabled planes? */ in skl_crtc_can_enable_sagv()
394 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
400 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) in skl_crtc_can_enable_sagv()
409 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in tgl_crtc_can_enable_sagv()
412 if (!crtc_state->hw.active) in tgl_crtc_can_enable_sagv()
417 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
419 if (wm->wm[0].enable && !wm->sagv.wm0.enable) in tgl_crtc_can_enable_sagv()
428 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_can_enable_sagv()
429 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_can_enable_sagv()
431 if (!i915->display.params.enable_sagv) in intel_crtc_can_enable_sagv()
444 bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) in intel_can_enable_sagv()
447 return bw_state->pipe_sagv_reject == 0; in intel_can_enable_sagv()
453 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_compute_sagv_mask()
463 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; in intel_compute_sagv_mask()
473 * that bw state since we have no convenient way to get at the in intel_compute_sagv_mask()
486 * normal (ie. non-SAGV) watermarks. in intel_compute_sagv_mask()
488 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) && in intel_compute_sagv_mask()
493 new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe); in intel_compute_sagv_mask()
495 new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe); in intel_compute_sagv_mask()
501 new_bw_state->active_pipes = in intel_compute_sagv_mask()
502 intel_calc_active_pipes(state, old_bw_state->active_pipes); in intel_compute_sagv_mask()
504 if (new_bw_state->active_pipes != old_bw_state->active_pipes) { in intel_compute_sagv_mask()
505 ret = intel_atomic_lock_global_state(&new_bw_state->base); in intel_compute_sagv_mask()
512 ret = intel_atomic_serialize_global_state(&new_bw_state->base); in intel_compute_sagv_mask()
515 } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) { in intel_compute_sagv_mask()
516 ret = intel_atomic_lock_global_state(&new_bw_state->base); in intel_compute_sagv_mask()
527 entry->start = start; in skl_ddb_entry_init()
528 entry->end = end; in skl_ddb_entry_init()
535 return DISPLAY_INFO(i915)->dbuf.size / in intel_dbuf_slice_size()
536 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask); in intel_dbuf_slice_size()
546 ddb->start = 0; in skl_ddb_entry_for_slices()
547 ddb->end = 0; in skl_ddb_entry_for_slices()
551 ddb->start = (ffs(slice_mask) - 1) * slice_size; in skl_ddb_entry_for_slices()
552 ddb->end = fls(slice_mask) * slice_size; in skl_ddb_entry_for_slices()
554 WARN_ON(ddb->start >= ddb->end); in skl_ddb_entry_for_slices()
555 WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size); in skl_ddb_entry_for_slices()
582 start_slice = entry->start / slice_size; in skl_ddb_dbuf_slice_mask()
583 end_slice = (entry->end - 1) / slice_size; in skl_ddb_dbuf_slice_mask()
599 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; in intel_crtc_ddb_weight()
602 if (!crtc_state->hw.active) in intel_crtc_ddb_weight()
622 to_i915(dbuf_state->base.state->base.dev); in intel_crtc_dbuf_weights()
630 int weight = dbuf_state->weight[pipe]; in intel_crtc_dbuf_weights()
636 * i.e no partial intersection), so it is enough to check for in intel_crtc_dbuf_weights()
639 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) in intel_crtc_dbuf_weights()
655 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_crtc_allocate_ddb()
663 enum pipe pipe = crtc->pipe; in skl_crtc_allocate_ddb()
670 if (new_dbuf_state->weight[pipe] == 0) { in skl_crtc_allocate_ddb()
671 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0); in skl_crtc_allocate_ddb()
675 dbuf_slice_mask = new_dbuf_state->slices[pipe]; in skl_crtc_allocate_ddb()
687 skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], in skl_crtc_allocate_ddb()
688 ddb_slices.start - mbus_offset + start, in skl_crtc_allocate_ddb()
689 ddb_slices.start - mbus_offset + end); in skl_crtc_allocate_ddb()
692 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && in skl_crtc_allocate_ddb()
693 skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe], in skl_crtc_allocate_ddb()
694 &new_dbuf_state->ddb[pipe])) in skl_crtc_allocate_ddb()
697 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); in skl_crtc_allocate_ddb()
701 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in skl_crtc_allocate_ddb()
709 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; in skl_crtc_allocate_ddb()
710 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; in skl_crtc_allocate_ddb()
712 drm_dbg_kms(&i915->drm, in skl_crtc_allocate_ddb()
713 … "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", in skl_crtc_allocate_ddb()
714 crtc->base.base.id, crtc->base.name, in skl_crtc_allocate_ddb()
715 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], in skl_crtc_allocate_ddb()
716 old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end, in skl_crtc_allocate_ddb()
717 new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end, in skl_crtc_allocate_ddb()
718 old_dbuf_state->active_pipes, new_dbuf_state->active_pipes); in skl_crtc_allocate_ddb()
726 u32 plane_pixel_rate, struct skl_wm_params *wp,
733 const struct skl_wm_params *wp,
738 const struct skl_wm_params *wp) in skl_wm_latency() argument
740 unsigned int latency = i915->display.wm.skl_latency[level]; in skl_wm_latency()
753 if (skl_needs_memory_bw_wa(i915) && wp && wp->x_tiled) in skl_wm_latency()
763 struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor); in skl_cursor_allocation()
764 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_cursor_allocation()
767 struct skl_wm_params wp; in skl_cursor_allocation() local
774 crtc_state->pixel_rate, &wp, 0, 0); in skl_cursor_allocation()
775 drm_WARN_ON(&i915->drm, ret); in skl_cursor_allocation()
777 for (level = 0; level < i915->display.wm.num_levels; level++) { in skl_cursor_allocation()
778 unsigned int latency = skl_wm_latency(i915, level, &wp); in skl_cursor_allocation()
780 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); in skl_cursor_allocation()
795 if (entry->end) in skl_ddb_entry_init_from_hw()
796 entry->end++; in skl_ddb_entry_init_from_hw()
807 struct intel_display *display = &i915->display; in skl_ddb_get_hw_plane_state()
810 /* Cursor doesn't support NV12/planar, so no extra calculation needed */ in skl_ddb_get_hw_plane_state()
839 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_pipe_ddb_get_hw_state()
841 enum pipe pipe = crtc->pipe; in skl_pipe_ddb_get_hw_state()
874 * as is from BSpec itself - that way it is at least easier
937 * as is from BSpec itself - that way it is at least easier
1342 * still here - we will need it once those additional constraints in icl_compute_dbuf_slices()
1369 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_compute_dbuf_slices()
1370 enum pipe pipe = crtc->pipe; in skl_compute_dbuf_slices()
1395 crtc_state->uapi.async_flip && in use_minimal_wm0_only()
1396 plane->async_flip; in use_minimal_wm0_only()
1418 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_total_relative_data_rate()
1419 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_total_relative_data_rate()
1427 data_rate += crtc_state->rel_data_rate[plane_id]; in skl_total_relative_data_rate()
1430 data_rate += crtc_state->rel_data_rate_y[plane_id]; in skl_total_relative_data_rate()
1441 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_wm_level()
1443 if (level == 0 && pipe_wm->use_sagv_wm) in skl_plane_wm_level()
1444 return &wm->sagv.wm0; in skl_plane_wm_level()
1446 return &wm->wm[level]; in skl_plane_wm_level()
1453 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_trans_wm()
1455 if (pipe_wm->use_sagv_wm) in skl_plane_trans_wm()
1456 return &wm->sagv.trans_wm; in skl_plane_trans_wm()
1458 return &wm->trans_wm; in skl_plane_trans_wm()
1476 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) in skl_check_wm_level()
1484 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || in skl_check_nv12_wm_level()
1485 uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) { in skl_check_nv12_wm_level()
1506 return level > 0 && !wm->wm[level].enable; in skl_need_wm_copy_wa()
1523 extra = min_t(u16, iter->size, in skl_allocate_plane_ddb()
1524 DIV64_U64_ROUND_UP(iter->size * data_rate, in skl_allocate_plane_ddb()
1525 iter->data_rate)); in skl_allocate_plane_ddb()
1526 iter->size -= extra; in skl_allocate_plane_ddb()
1527 iter->data_rate -= data_rate; in skl_allocate_plane_ddb()
1535 size = wm->min_ddb_alloc + extra; in skl_allocate_plane_ddb()
1537 iter->start = skl_ddb_entry_init(ddb, iter->start, in skl_allocate_plane_ddb()
1538 iter->start + size); in skl_allocate_plane_ddb()
1545 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_crtc_allocate_plane_ddb()
1550 const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; in skl_crtc_allocate_plane_ddb()
1552 int num_active = hweight8(dbuf_state->active_pipes); in skl_crtc_allocate_plane_ddb()
1560 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); in skl_crtc_allocate_plane_ddb()
1561 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_crtc_allocate_plane_ddb()
1562 memset(crtc_state->wm.skl.plane_min_ddb, 0, in skl_crtc_allocate_plane_ddb()
1563 sizeof(crtc_state->wm.skl.plane_min_ddb)); in skl_crtc_allocate_plane_ddb()
1564 memset(crtc_state->wm.skl.plane_interim_ddb, 0, in skl_crtc_allocate_plane_ddb()
1565 sizeof(crtc_state->wm.skl.plane_interim_ddb)); in skl_crtc_allocate_plane_ddb()
1567 if (!crtc_state->hw.active) in skl_crtc_allocate_plane_ddb()
1570 iter.start = alloc->start; in skl_crtc_allocate_plane_ddb()
1577 iter.size -= cursor_size; in skl_crtc_allocate_plane_ddb()
1578 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR], in skl_crtc_allocate_plane_ddb()
1579 alloc->end - cursor_size, alloc->end); in skl_crtc_allocate_plane_ddb()
1587 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { in skl_crtc_allocate_plane_ddb()
1591 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1595 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1597 if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) { in skl_crtc_allocate_plane_ddb()
1598 drm_WARN_ON(&i915->drm, in skl_crtc_allocate_plane_ddb()
1599 wm->wm[level].min_ddb_alloc != U16_MAX); in skl_crtc_allocate_plane_ddb()
1606 blocks += wm->wm[level].min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1607 blocks += wm->uv_wm[level].min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1611 iter.size -= blocks; in skl_crtc_allocate_plane_ddb()
1617 drm_dbg_kms(&i915->drm, in skl_crtc_allocate_plane_ddb()
1619 drm_dbg_kms(&i915->drm, "minimum required %d/%d\n", in skl_crtc_allocate_plane_ddb()
1621 return -EINVAL; in skl_crtc_allocate_plane_ddb()
1635 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1637 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_crtc_allocate_plane_ddb()
1638 u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1640 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1642 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1648 crtc_state->nv12_planes & BIT(plane_id)) { in skl_crtc_allocate_plane_ddb()
1649 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], in skl_crtc_allocate_plane_ddb()
1650 crtc_state->rel_data_rate_y[plane_id]); in skl_crtc_allocate_plane_ddb()
1651 skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level], in skl_crtc_allocate_plane_ddb()
1652 crtc_state->rel_data_rate[plane_id]); in skl_crtc_allocate_plane_ddb()
1654 skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], in skl_crtc_allocate_plane_ddb()
1655 crtc_state->rel_data_rate[plane_id]); in skl_crtc_allocate_plane_ddb()
1659 *min_ddb = wm->wm[0].min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1660 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1663 drm_WARN_ON(&i915->drm, iter.size != 0 || iter.data_rate != 0); in skl_crtc_allocate_plane_ddb()
1671 for (level++; level < i915->display.wm.num_levels; level++) { in skl_crtc_allocate_plane_ddb()
1674 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1676 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_crtc_allocate_plane_ddb()
1678 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1681 crtc_state->nv12_planes & BIT(plane_id)) in skl_crtc_allocate_plane_ddb()
1682 skl_check_nv12_wm_level(&wm->wm[level], in skl_crtc_allocate_plane_ddb()
1683 &wm->uv_wm[level], in skl_crtc_allocate_plane_ddb()
1686 skl_check_wm_level(&wm->wm[level], ddb); in skl_crtc_allocate_plane_ddb()
1689 wm->wm[level].blocks = wm->wm[level - 1].blocks; in skl_crtc_allocate_plane_ddb()
1690 wm->wm[level].lines = wm->wm[level - 1].lines; in skl_crtc_allocate_plane_ddb()
1691 wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines; in skl_crtc_allocate_plane_ddb()
1702 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1704 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_crtc_allocate_plane_ddb()
1706 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1708 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1711 crtc_state->nv12_planes & BIT(plane_id)) { in skl_crtc_allocate_plane_ddb()
1712 skl_check_wm_level(&wm->trans_wm, ddb_y); in skl_crtc_allocate_plane_ddb()
1716 skl_check_wm_level(&wm->trans_wm, ddb); in skl_crtc_allocate_plane_ddb()
1719 skl_check_wm_level(&wm->sagv.wm0, ddb); in skl_crtc_allocate_plane_ddb()
1721 *interim_ddb = wm->sagv.wm0.min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1723 skl_check_wm_level(&wm->sagv.trans_wm, ddb); in skl_crtc_allocate_plane_ddb()
1774 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_get_linetime_us()
1779 if (!crtc_state->hw.active) in intel_get_linetime_us()
1782 pixel_rate = crtc_state->pixel_rate; in intel_get_linetime_us()
1784 if (drm_WARN_ON(&i915->drm, pixel_rate == 0)) in intel_get_linetime_us()
1787 crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal; in intel_get_linetime_us()
1797 u32 plane_pixel_rate, struct skl_wm_params *wp, in skl_compute_wm_params() argument
1800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_compute_wm_params()
1802 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_compute_wm_params()
1808 drm_dbg_kms(&i915->drm, in skl_compute_wm_params()
1810 return -EINVAL; in skl_compute_wm_params()
1813 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; in skl_compute_wm_params()
1814 wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED && in skl_compute_wm_params()
1816 wp->rc_surface = intel_fb_is_ccs_modifier(modifier); in skl_compute_wm_params()
1817 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); in skl_compute_wm_params()
1819 wp->width = width; in skl_compute_wm_params()
1820 if (color_plane == 1 && wp->is_planar) in skl_compute_wm_params()
1821 wp->width /= 2; in skl_compute_wm_params()
1823 wp->cpp = format->cpp[color_plane]; in skl_compute_wm_params()
1824 wp->plane_pixel_rate = plane_pixel_rate; in skl_compute_wm_params()
1827 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1) in skl_compute_wm_params()
1828 wp->dbuf_block_size = 256; in skl_compute_wm_params()
1830 wp->dbuf_block_size = 512; in skl_compute_wm_params()
1833 switch (wp->cpp) { in skl_compute_wm_params()
1835 wp->y_min_scanlines = 16; in skl_compute_wm_params()
1838 wp->y_min_scanlines = 8; in skl_compute_wm_params()
1841 wp->y_min_scanlines = 4; in skl_compute_wm_params()
1844 MISSING_CASE(wp->cpp); in skl_compute_wm_params()
1845 return -EINVAL; in skl_compute_wm_params()
1848 wp->y_min_scanlines = 4; in skl_compute_wm_params()
1852 wp->y_min_scanlines *= 2; in skl_compute_wm_params()
1854 wp->plane_bytes_per_line = wp->width * wp->cpp; in skl_compute_wm_params()
1855 if (wp->y_tiled) { in skl_compute_wm_params()
1856 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line * in skl_compute_wm_params()
1857 wp->y_min_scanlines, in skl_compute_wm_params()
1858 wp->dbuf_block_size); in skl_compute_wm_params()
1865 wp->plane_blocks_per_line = div_fixed16(interm_pbpl, in skl_compute_wm_params()
1866 wp->y_min_scanlines); in skl_compute_wm_params()
1868 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, in skl_compute_wm_params()
1869 wp->dbuf_block_size); in skl_compute_wm_params()
1871 if (!wp->x_tiled || DISPLAY_VER(i915) >= 10) in skl_compute_wm_params()
1874 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); in skl_compute_wm_params()
1877 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines, in skl_compute_wm_params()
1878 wp->plane_blocks_per_line); in skl_compute_wm_params()
1880 wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state)); in skl_compute_wm_params()
1888 struct skl_wm_params *wp, int color_plane) in skl_compute_plane_wm_params() argument
1890 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_compute_plane_wm_params()
1896 * GTT mapping), hence no need to account for rotation here. in skl_compute_plane_wm_params()
1898 width = drm_rect_width(&plane_state->uapi.src) >> 16; in skl_compute_plane_wm_params()
1901 fb->format, fb->modifier, in skl_compute_plane_wm_params()
1902 plane_state->hw.rotation, in skl_compute_plane_wm_params()
1904 wp, color_plane, in skl_compute_plane_wm_params()
1905 plane_state->uapi.src.x1); in skl_compute_plane_wm_params()
1929 return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR; in xe3_auto_min_alloc_capable()
1936 const struct skl_wm_params *wp, in skl_compute_plane_wm() argument
1940 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_compute_plane_wm()
1948 result->min_ddb_alloc = U16_MAX; in skl_compute_plane_wm()
1952 method1 = skl_wm_method1(i915, wp->plane_pixel_rate, in skl_compute_plane_wm()
1953 wp->cpp, latency, wp->dbuf_block_size); in skl_compute_plane_wm()
1954 method2 = skl_wm_method2(wp->plane_pixel_rate, in skl_compute_plane_wm()
1955 crtc_state->hw.pipe_mode.crtc_htotal, in skl_compute_plane_wm()
1957 wp->plane_blocks_per_line); in skl_compute_plane_wm()
1959 if (wp->y_tiled) { in skl_compute_plane_wm()
1960 selected_result = max_fixed16(method2, wp->y_tile_minimum); in skl_compute_plane_wm()
1962 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal / in skl_compute_plane_wm()
1963 wp->dbuf_block_size < 1) && in skl_compute_plane_wm()
1964 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { in skl_compute_plane_wm()
1966 } else if (latency >= wp->linetime_us) { in skl_compute_plane_wm()
1998 fixed16_to_u32_round_up(wp->plane_blocks_per_line)); in skl_compute_plane_wm()
2000 wp->plane_blocks_per_line); in skl_compute_plane_wm()
2004 if (level == 0 && wp->rc_surface) in skl_compute_plane_wm()
2005 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); in skl_compute_plane_wm()
2009 if (wp->y_tiled) { in skl_compute_plane_wm()
2010 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum); in skl_compute_plane_wm()
2011 lines += wp->y_min_scanlines; in skl_compute_plane_wm()
2022 if (result_prev->blocks > blocks) in skl_compute_plane_wm()
2023 blocks = result_prev->blocks; in skl_compute_plane_wm()
2028 if (wp->y_tiled) { in skl_compute_plane_wm()
2031 if (lines % wp->y_min_scanlines == 0) in skl_compute_plane_wm()
2032 extra_lines = wp->y_min_scanlines; in skl_compute_plane_wm()
2034 extra_lines = wp->y_min_scanlines * 2 - in skl_compute_plane_wm()
2035 lines % wp->y_min_scanlines; in skl_compute_plane_wm()
2038 wp->plane_blocks_per_line); in skl_compute_plane_wm()
2049 result->min_ddb_alloc = U16_MAX; in skl_compute_plane_wm()
2059 result->blocks = blocks; in skl_compute_plane_wm()
2060 result->lines = lines; in skl_compute_plane_wm()
2061 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ in skl_compute_plane_wm()
2062 result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; in skl_compute_plane_wm()
2063 result->enable = true; in skl_compute_plane_wm()
2064 result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level); in skl_compute_plane_wm()
2066 if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us) in skl_compute_plane_wm()
2067 result->can_sagv = latency >= i915->display.sagv.block_time_us; in skl_compute_plane_wm()
2076 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_compute_wm_levels()
2080 for (level = 0; level < i915->display.wm.num_levels; level++) { in skl_compute_wm_levels()
2096 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in tgl_compute_sagv_wm()
2097 struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0; in tgl_compute_sagv_wm()
2098 struct skl_wm_level *levels = plane_wm->wm; in tgl_compute_sagv_wm()
2101 if (i915->display.sagv.block_time_us) in tgl_compute_sagv_wm()
2102 latency = i915->display.sagv.block_time_us + in tgl_compute_sagv_wm()
2113 const struct skl_wm_params *wp) in skl_compute_transition_wm() argument
2145 * letters. The value wm_l0->blocks is actually Result Blocks, but in skl_compute_transition_wm()
2152 wm0_blocks = wm0->blocks - 1; in skl_compute_transition_wm()
2154 if (wp->y_tiled) { in skl_compute_transition_wm()
2156 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum); in skl_compute_transition_wm()
2168 trans_wm->blocks = blocks; in skl_compute_transition_wm()
2169 trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1); in skl_compute_transition_wm()
2170 trans_wm->enable = true; in skl_compute_transition_wm()
2177 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_build_plane_wm_single()
2178 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_build_plane_wm_single()
2179 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; in skl_build_plane_wm_single()
2188 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm); in skl_build_plane_wm_single()
2190 skl_compute_transition_wm(i915, &wm->trans_wm, in skl_build_plane_wm_single()
2191 &wm->wm[0], &wm_params); in skl_build_plane_wm_single()
2196 skl_compute_transition_wm(i915, &wm->sagv.trans_wm, in skl_build_plane_wm_single()
2197 &wm->sagv.wm0, &wm_params); in skl_build_plane_wm_single()
2207 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; in skl_build_plane_wm_uv()
2211 wm->is_planar = true; in skl_build_plane_wm_uv()
2219 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm); in skl_build_plane_wm_uv()
2227 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in skl_build_plane_wm()
2228 enum plane_id plane_id = plane->id; in skl_build_plane_wm()
2229 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in skl_build_plane_wm()
2230 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_build_plane_wm()
2243 if (fb->format->is_yuv && fb->format->num_planes > 1) { in skl_build_plane_wm()
2256 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in icl_build_plane_wm()
2257 struct drm_i915_private *i915 = to_i915(plane->base.dev); in icl_build_plane_wm()
2258 enum plane_id plane_id = plane->id; in icl_build_plane_wm()
2259 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in icl_build_plane_wm()
2263 if (plane_state->planar_slave) in icl_build_plane_wm()
2268 if (plane_state->planar_linked_plane) { in icl_build_plane_wm()
2269 const struct drm_framebuffer *fb = plane_state->hw.fb; in icl_build_plane_wm()
2271 drm_WARN_ON(&i915->drm, in icl_build_plane_wm()
2273 drm_WARN_ON(&i915->drm, !fb->format->is_yuv || in icl_build_plane_wm()
2274 fb->format->num_planes == 1); in icl_build_plane_wm()
2277 plane_state->planar_linked_plane, 0); in icl_build_plane_wm()
2300 &crtc_state->hw.adjusted_mode; in skl_is_vblank_too_short()
2302 /* FIXME missing scaler and DSC pre-fill time */ in skl_is_vblank_too_short()
2303 return crtc_state->framestart_delay + in skl_is_vblank_too_short()
2306 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; in skl_is_vblank_too_short()
2311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_max_wm0_lines()
2316 const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_max_wm0_lines()
2319 wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines); in skl_max_wm0_lines()
2328 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_max_wm_level_for_vblank()
2329 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_max_wm_level_for_vblank()
2332 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { in skl_max_wm_level_for_vblank()
2348 return -EINVAL; in skl_max_wm_level_for_vblank()
2353 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_wm_check_vblank()
2354 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_wm_check_vblank()
2357 if (!crtc_state->hw.active) in skl_wm_check_vblank()
2370 crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1; in skl_wm_check_vblank()
2372 for (level++; level < i915->display.wm.num_levels; level++) { in skl_wm_check_vblank()
2377 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_wm_check_vblank()
2383 wm->wm[level].enable = false; in skl_wm_check_vblank()
2384 wm->uv_wm[level].enable = false; in skl_wm_check_vblank()
2389 i915->display.sagv.block_time_us && in skl_wm_check_vblank()
2391 i915->display.sagv.block_time_us)) { in skl_wm_check_vblank()
2396 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_wm_check_vblank()
2398 wm->sagv.wm0.enable = false; in skl_wm_check_vblank()
2399 wm->sagv.trans_wm.enable = false; in skl_wm_check_vblank()
2409 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_build_pipe_wm()
2418 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc in skl_build_pipe_wm()
2422 if (plane->pipe != crtc->pipe) in skl_build_pipe_wm()
2433 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; in skl_build_pipe_wm()
2441 return l1->enable == l2->enable && in skl_wm_level_equals()
2442 l1->ignore_lines == l2->ignore_lines && in skl_wm_level_equals()
2443 l1->lines == l2->lines && in skl_wm_level_equals()
2444 l1->blocks == l2->blocks && in skl_wm_level_equals()
2445 l1->auto_min_alloc_wm_enable == l2->auto_min_alloc_wm_enable; in skl_wm_level_equals()
2452 struct intel_display *display = &i915->display; in skl_plane_wm_equals()
2455 for (level = 0; level < display->wm.num_levels; level++) { in skl_plane_wm_equals()
2461 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) in skl_plane_wm_equals()
2465 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && in skl_plane_wm_equals()
2466 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) && in skl_plane_wm_equals()
2467 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm); in skl_plane_wm_equals()
2473 return a->start < b->end && b->start < a->end; in skl_ddb_entries_overlap()
2479 if (a->end && b->end) { in skl_ddb_entry_union()
2480 a->start = min(a->start, b->start); in skl_ddb_entry_union()
2481 a->end = max(a->end, b->end); in skl_ddb_entry_union()
2482 } else if (b->end) { in skl_ddb_entry_union()
2483 a->start = b->start; in skl_ddb_entry_union()
2484 a->end = b->end; in skl_ddb_entry_union()
2507 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_ddb_add_affected_planes()
2514 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in skl_ddb_add_affected_planes()
2516 enum plane_id plane_id = plane->id; in skl_ddb_add_affected_planes()
2518 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id], in skl_ddb_add_affected_planes()
2519 &new_crtc_state->wm.skl.plane_ddb[plane_id]) && in skl_ddb_add_affected_planes()
2520 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_ddb_add_affected_planes()
2521 &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) in skl_ddb_add_affected_planes()
2524 if (new_crtc_state->do_async_flip) { in skl_ddb_add_affected_planes()
2525 drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n", in skl_ddb_add_affected_planes()
2526 plane->base.base.id, plane->base.name); in skl_ddb_add_affected_planes()
2527 return -EINVAL; in skl_ddb_add_affected_planes()
2534 new_crtc_state->update_planes |= BIT(plane_id); in skl_ddb_add_affected_planes()
2535 new_crtc_state->async_flip_planes = 0; in skl_ddb_add_affected_planes()
2536 new_crtc_state->do_async_flip = false; in skl_ddb_add_affected_planes()
2544 struct drm_i915_private *i915 = to_i915(dbuf_state->base.state->base.dev); in intel_dbuf_enabled_slices()
2555 enabled_slices |= dbuf_state->slices[pipe]; in intel_dbuf_enabled_slices()
2564 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_compute_ddb()
2583 new_dbuf_state->active_pipes = in skl_compute_ddb()
2584 intel_calc_active_pipes(state, old_dbuf_state->active_pipes); in skl_compute_ddb()
2586 if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { in skl_compute_ddb()
2587 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); in skl_compute_ddb()
2593 new_dbuf_state->joined_mbus = in skl_compute_ddb()
2594 adlp_check_mbus_joined(new_dbuf_state->active_pipes); in skl_compute_ddb()
2596 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { in skl_compute_ddb()
2597 ret = intel_cdclk_state_set_joined_mbus(state, new_dbuf_state->joined_mbus); in skl_compute_ddb()
2603 for_each_intel_crtc(&i915->drm, crtc) { in skl_compute_ddb()
2604 enum pipe pipe = crtc->pipe; in skl_compute_ddb()
2606 new_dbuf_state->slices[pipe] = in skl_compute_ddb()
2607 skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes, in skl_compute_ddb()
2608 new_dbuf_state->joined_mbus); in skl_compute_ddb()
2610 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) in skl_compute_ddb()
2613 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); in skl_compute_ddb()
2618 new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state); in skl_compute_ddb()
2620 if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices || in skl_compute_ddb()
2621 old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { in skl_compute_ddb()
2622 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base); in skl_compute_ddb()
2626 drm_dbg_kms(&i915->drm, in skl_compute_ddb()
2627 "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n", in skl_compute_ddb()
2628 old_dbuf_state->enabled_slices, in skl_compute_ddb()
2629 new_dbuf_state->enabled_slices, in skl_compute_ddb()
2630 DISPLAY_INFO(i915)->dbuf.slice_mask, in skl_compute_ddb()
2631 str_yes_no(old_dbuf_state->joined_mbus), in skl_compute_ddb()
2632 str_yes_no(new_dbuf_state->joined_mbus)); in skl_compute_ddb()
2636 enum pipe pipe = crtc->pipe; in skl_compute_ddb()
2638 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state); in skl_compute_ddb()
2640 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe]) in skl_compute_ddb()
2643 ret = intel_atomic_lock_global_state(&new_dbuf_state->base); in skl_compute_ddb()
2648 for_each_intel_crtc(&i915->drm, crtc) { in skl_compute_ddb()
2675 struct drm_i915_private *i915 = to_i915(state->base.dev); in skl_print_wm_changes()
2689 old_pipe_wm = &old_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
2690 new_pipe_wm = &new_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
2692 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in skl_print_wm_changes()
2693 enum plane_id plane_id = plane->id; in skl_print_wm_changes()
2696 old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; in skl_print_wm_changes()
2697 new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; in skl_print_wm_changes()
2702 drm_dbg_kms(&i915->drm, in skl_print_wm_changes()
2703 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n", in skl_print_wm_changes()
2704 plane->base.base.id, plane->base.name, in skl_print_wm_changes()
2705 old->start, old->end, new->start, new->end, in skl_print_wm_changes()
2709 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in skl_print_wm_changes()
2710 enum plane_id plane_id = plane->id; in skl_print_wm_changes()
2713 old_wm = &old_pipe_wm->planes[plane_id]; in skl_print_wm_changes()
2714 new_wm = &new_pipe_wm->planes[plane_id]; in skl_print_wm_changes()
2719 drm_dbg_kms(&i915->drm, in skl_print_wm_changes()
2721 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n", in skl_print_wm_changes()
2722 plane->base.base.id, plane->base.name, in skl_print_wm_changes()
2723 enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), in skl_print_wm_changes()
2724 enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), in skl_print_wm_changes()
2725 enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), in skl_print_wm_changes()
2726 enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), in skl_print_wm_changes()
2727 enast(old_wm->trans_wm.enable), in skl_print_wm_changes()
2728 enast(old_wm->sagv.wm0.enable), in skl_print_wm_changes()
2729 enast(old_wm->sagv.trans_wm.enable), in skl_print_wm_changes()
2730 enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), in skl_print_wm_changes()
2731 enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), in skl_print_wm_changes()
2732 enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), in skl_print_wm_changes()
2733 enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), in skl_print_wm_changes()
2734 enast(new_wm->trans_wm.enable), in skl_print_wm_changes()
2735 enast(new_wm->sagv.wm0.enable), in skl_print_wm_changes()
2736 enast(new_wm->sagv.trans_wm.enable)); in skl_print_wm_changes()
2738 drm_dbg_kms(&i915->drm, in skl_print_wm_changes()
2740 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n", in skl_print_wm_changes()
2741 plane->base.base.id, plane->base.name, in skl_print_wm_changes()
2742 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, in skl_print_wm_changes()
2743 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, in skl_print_wm_changes()
2744 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, in skl_print_wm_changes()
2745 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, in skl_print_wm_changes()
2746 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, in skl_print_wm_changes()
2747 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, in skl_print_wm_changes()
2748 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, in skl_print_wm_changes()
2749 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, in skl_print_wm_changes()
2750 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines, in skl_print_wm_changes()
2751 enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines, in skl_print_wm_changes()
2752 enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines, in skl_print_wm_changes()
2753 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, in skl_print_wm_changes()
2754 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, in skl_print_wm_changes()
2755 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, in skl_print_wm_changes()
2756 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, in skl_print_wm_changes()
2757 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, in skl_print_wm_changes()
2758 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, in skl_print_wm_changes()
2759 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, in skl_print_wm_changes()
2760 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, in skl_print_wm_changes()
2761 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines, in skl_print_wm_changes()
2762 enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines, in skl_print_wm_changes()
2763 enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines); in skl_print_wm_changes()
2765 drm_dbg_kms(&i915->drm, in skl_print_wm_changes()
2767 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", in skl_print_wm_changes()
2768 plane->base.base.id, plane->base.name, in skl_print_wm_changes()
2769 old_wm->wm[0].blocks, old_wm->wm[1].blocks, in skl_print_wm_changes()
2770 old_wm->wm[2].blocks, old_wm->wm[3].blocks, in skl_print_wm_changes()
2771 old_wm->wm[4].blocks, old_wm->wm[5].blocks, in skl_print_wm_changes()
2772 old_wm->wm[6].blocks, old_wm->wm[7].blocks, in skl_print_wm_changes()
2773 old_wm->trans_wm.blocks, in skl_print_wm_changes()
2774 old_wm->sagv.wm0.blocks, in skl_print_wm_changes()
2775 old_wm->sagv.trans_wm.blocks, in skl_print_wm_changes()
2776 new_wm->wm[0].blocks, new_wm->wm[1].blocks, in skl_print_wm_changes()
2777 new_wm->wm[2].blocks, new_wm->wm[3].blocks, in skl_print_wm_changes()
2778 new_wm->wm[4].blocks, new_wm->wm[5].blocks, in skl_print_wm_changes()
2779 new_wm->wm[6].blocks, new_wm->wm[7].blocks, in skl_print_wm_changes()
2780 new_wm->trans_wm.blocks, in skl_print_wm_changes()
2781 new_wm->sagv.wm0.blocks, in skl_print_wm_changes()
2782 new_wm->sagv.trans_wm.blocks); in skl_print_wm_changes()
2784 drm_dbg_kms(&i915->drm, in skl_print_wm_changes()
2786 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n", in skl_print_wm_changes()
2787 plane->base.base.id, plane->base.name, in skl_print_wm_changes()
2788 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, in skl_print_wm_changes()
2789 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, in skl_print_wm_changes()
2790 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, in skl_print_wm_changes()
2791 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, in skl_print_wm_changes()
2792 old_wm->trans_wm.min_ddb_alloc, in skl_print_wm_changes()
2793 old_wm->sagv.wm0.min_ddb_alloc, in skl_print_wm_changes()
2794 old_wm->sagv.trans_wm.min_ddb_alloc, in skl_print_wm_changes()
2795 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, in skl_print_wm_changes()
2796 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, in skl_print_wm_changes()
2797 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, in skl_print_wm_changes()
2798 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, in skl_print_wm_changes()
2799 new_wm->trans_wm.min_ddb_alloc, in skl_print_wm_changes()
2800 new_wm->sagv.wm0.min_ddb_alloc, in skl_print_wm_changes()
2801 new_wm->sagv.trans_wm.min_ddb_alloc); in skl_print_wm_changes()
2813 for (level = 0; level < display->wm.num_levels; level++) { in skl_plane_selected_wm_equals()
2819 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level), in skl_plane_selected_wm_equals()
2820 skl_plane_wm_level(new_pipe_wm, plane->id, level))) in skl_plane_selected_wm_equals()
2825 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id]; in skl_plane_selected_wm_equals()
2826 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id]; in skl_plane_selected_wm_equals()
2828 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) || in skl_plane_selected_wm_equals()
2829 !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm)) in skl_plane_selected_wm_equals()
2833 return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id), in skl_plane_selected_wm_equals()
2834 skl_plane_trans_wm(new_pipe_wm, plane->id)); in skl_plane_selected_wm_equals()
2862 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_wm_add_affected_planes()
2869 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in skl_wm_add_affected_planes()
2871 enum plane_id plane_id = plane->id; in skl_wm_add_affected_planes()
2876 * is non-zero, whereas we want all disabled planes to in skl_wm_add_affected_planes()
2883 &old_crtc_state->wm.skl.optimal, in skl_wm_add_affected_planes()
2884 &new_crtc_state->wm.skl.optimal)) in skl_wm_add_affected_planes()
2887 if (new_crtc_state->do_async_flip) { in skl_wm_add_affected_planes()
2888 drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n", in skl_wm_add_affected_planes()
2889 plane->base.base.id, plane->base.name); in skl_wm_add_affected_planes()
2890 return -EINVAL; in skl_wm_add_affected_planes()
2897 new_crtc_state->update_planes |= BIT(plane_id); in skl_wm_add_affected_planes()
2898 new_crtc_state->async_flip_planes = 0; in skl_wm_add_affected_planes()
2899 new_crtc_state->do_async_flip = false; in skl_wm_add_affected_planes()
2919 struct drm_i915_private *i915 = to_i915(display->drm); in intel_program_dpkgc_latency()
2933 if (!new_crtc_state->vrr.enable || in intel_program_dpkgc_latency()
2934 (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && in intel_program_dpkgc_latency()
2935 new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)) in intel_program_dpkgc_latency()
2938 max_linetime = max(new_crtc_state->linetime, max_linetime); in intel_program_dpkgc_latency()
2943 display->sagv.block_time_us; in intel_program_dpkgc_latency()
3009 level->enable = val & PLANE_WM_EN; in skl_wm_level_from_reg_val()
3010 level->ignore_lines = val & PLANE_WM_IGNORE_LINES; in skl_wm_level_from_reg_val()
3011 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); in skl_wm_level_from_reg_val()
3012 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); in skl_wm_level_from_reg_val()
3013 level->auto_min_alloc_wm_enable = DISPLAY_VER(display) >= 30 ? in skl_wm_level_from_reg_val()
3021 enum pipe pipe = crtc->pipe; in skl_pipe_wm_get_hw_state()
3027 struct skl_plane_wm *wm = &out->planes[plane_id]; in skl_pipe_wm_get_hw_state()
3029 for (level = 0; level < display->wm.num_levels; level++) { in skl_pipe_wm_get_hw_state()
3035 skl_wm_level_from_reg_val(display, val, &wm->wm[level]); in skl_pipe_wm_get_hw_state()
3043 skl_wm_level_from_reg_val(display, val, &wm->trans_wm); in skl_pipe_wm_get_hw_state()
3051 skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0); in skl_pipe_wm_get_hw_state()
3058 skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm); in skl_pipe_wm_get_hw_state()
3060 wm->sagv.wm0 = wm->wm[0]; in skl_pipe_wm_get_hw_state()
3061 wm->sagv.trans_wm = wm->trans_wm; in skl_pipe_wm_get_hw_state()
3068 struct intel_display *display = &i915->display; in skl_wm_get_hw_state()
3070 to_intel_dbuf_state(i915->display.dbuf.obj.state); in skl_wm_get_hw_state()
3074 dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; in skl_wm_get_hw_state()
3076 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); in skl_wm_get_hw_state()
3078 for_each_intel_crtc(display->drm, crtc) { in skl_wm_get_hw_state()
3080 to_intel_crtc_state(crtc->base.state); in skl_wm_get_hw_state()
3081 enum pipe pipe = crtc->pipe; in skl_wm_get_hw_state()
3086 memset(&crtc_state->wm.skl.optimal, 0, in skl_wm_get_hw_state()
3087 sizeof(crtc_state->wm.skl.optimal)); in skl_wm_get_hw_state()
3088 if (crtc_state->hw.active) in skl_wm_get_hw_state()
3089 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); in skl_wm_get_hw_state()
3090 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; in skl_wm_get_hw_state()
3092 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); in skl_wm_get_hw_state()
3096 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_wm_get_hw_state()
3098 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_wm_get_hw_state()
3100 &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_wm_get_hw_state()
3102 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; in skl_wm_get_hw_state()
3104 if (!crtc_state->hw.active) in skl_wm_get_hw_state()
3107 skl_ddb_get_hw_plane_state(i915, crtc->pipe, in skl_wm_get_hw_state()
3111 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); in skl_wm_get_hw_state()
3112 skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); in skl_wm_get_hw_state()
3115 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state); in skl_wm_get_hw_state()
3121 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, in skl_wm_get_hw_state()
3122 dbuf_state->joined_mbus); in skl_wm_get_hw_state()
3124 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; in skl_wm_get_hw_state()
3125 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; in skl_wm_get_hw_state()
3128 dbuf_state->slices[pipe] = in skl_wm_get_hw_state()
3129 skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb); in skl_wm_get_hw_state()
3131 drm_dbg_kms(display->drm, in skl_wm_get_hw_state()
3132 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n", in skl_wm_get_hw_state()
3133 crtc->base.base.id, crtc->base.name, in skl_wm_get_hw_state()
3134 dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start, in skl_wm_get_hw_state()
3135 dbuf_state->ddb[pipe].end, dbuf_state->active_pipes, in skl_wm_get_hw_state()
3136 str_yes_no(dbuf_state->joined_mbus)); in skl_wm_get_hw_state()
3139 dbuf_state->enabled_slices = display->dbuf.enabled_slices; in skl_wm_get_hw_state()
3144 return i915->display.wm.ipc_enabled; in skl_watermark_ipc_enabled()
3166 return i915->dram_info.symmetric_memory; in skl_watermark_ipc_can_enable()
3176 i915->display.wm.ipc_enabled = skl_watermark_ipc_can_enable(i915); in skl_watermark_ipc_init()
3185 bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed; in adjust_wm_latency()
3216 * WA Level-0 adjustment for 16GB DIMMs: SKL+ in adjust_wm_latency()
3227 int num_levels = i915->display.wm.num_levels; in mtl_read_wm_latency()
3247 int num_levels = i915->display.wm.num_levels; in skl_read_wm_latency()
3255 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); in skl_read_wm_latency()
3257 drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret); in skl_read_wm_latency()
3268 ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL); in skl_read_wm_latency()
3270 drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret); in skl_read_wm_latency()
3284 struct intel_display *display = &i915->display; in skl_setup_wm_latency()
3287 display->wm.num_levels = 6; in skl_setup_wm_latency()
3289 display->wm.num_levels = 8; in skl_setup_wm_latency()
3292 mtl_read_wm_latency(i915, display->wm.skl_latency); in skl_setup_wm_latency()
3294 skl_read_wm_latency(i915, display->wm.skl_latency); in skl_setup_wm_latency()
3296 intel_print_wm_latency(i915, "Gen9 Plane", display->wm.skl_latency); in skl_setup_wm_latency()
3303 dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL); in intel_dbuf_duplicate_state()
3307 return &dbuf_state->base; in intel_dbuf_duplicate_state()
3324 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_atomic_get_dbuf_state()
3327 dbuf_state = intel_atomic_get_global_obj_state(state, &i915->display.dbuf.obj); in intel_atomic_get_dbuf_state()
3336 struct intel_display *display = &i915->display; in intel_dbuf_init()
3341 return -ENOMEM; in intel_dbuf_init()
3343 intel_atomic_global_obj_init(display, &display->dbuf.obj, in intel_dbuf_init()
3344 &dbuf_state->base, &intel_dbuf_funcs); in intel_dbuf_init()
3371 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in pipe_mbus_dbox_ctl()
3384 val |= dbuf_state->joined_mbus ? in pipe_mbus_dbox_ctl()
3387 /* Wa_22010947358:adl-p */ in pipe_mbus_dbox_ctl()
3388 val |= dbuf_state->joined_mbus ? in pipe_mbus_dbox_ctl()
3407 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes)) in pipe_mbus_dbox_ctl()
3421 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, dbuf_state->active_pipes) in pipe_mbus_dbox_ctl_update()
3422 intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), in pipe_mbus_dbox_ctl_update()
3428 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_mbus_dbox_update()
3437 (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && in intel_mbus_dbox_update()
3438 new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) in intel_mbus_dbox_update()
3453 dbuf_state->mdclk_cdclk_ratio = ratio; in intel_dbuf_state_set_mdclk_cdclk_ratio()
3455 return intel_atomic_lock_global_state(&dbuf_state->base); in intel_dbuf_state_set_mdclk_cdclk_ratio()
3461 struct intel_display *display = &i915->display; in intel_dbuf_mdclk_cdclk_ratio_update()
3469 MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); in intel_dbuf_mdclk_cdclk_ratio_update()
3474 drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n", in intel_dbuf_mdclk_cdclk_ratio_update()
3480 DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); in intel_dbuf_mdclk_cdclk_ratio_update()
3485 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dbuf_mdclk_min_tracker_update()
3494 mdclk_cdclk_ratio = old_dbuf_state->mdclk_cdclk_ratio; in intel_dbuf_mdclk_min_tracker_update()
3497 mdclk_cdclk_ratio = new_dbuf_state->mdclk_cdclk_ratio; in intel_dbuf_mdclk_min_tracker_update()
3501 new_dbuf_state->joined_mbus); in intel_dbuf_mdclk_min_tracker_update()
3508 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_mbus_joined_pipe()
3509 enum pipe pipe = ffs(dbuf_state->active_pipes) - 1; in intel_mbus_joined_pipe()
3513 drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus); in intel_mbus_joined_pipe()
3514 drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes)); in intel_mbus_joined_pipe()
3531 if (dbuf_state->joined_mbus) in mbus_ctl_join_update()
3549 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dbuf_mbus_join_update()
3555 drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n", in intel_dbuf_mbus_join_update()
3556 str_yes_no(old_dbuf_state->joined_mbus), in intel_dbuf_mbus_join_update()
3557 str_yes_no(new_dbuf_state->joined_mbus), in intel_dbuf_mbus_join_update()
3573 if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) { in intel_dbuf_mbus_pre_ddb_update()
3576 WARN_ON(!new_dbuf_state->base.changed); in intel_dbuf_mbus_pre_ddb_update()
3595 if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) { in intel_dbuf_mbus_post_ddb_update()
3598 WARN_ON(!new_dbuf_state->base.changed); in intel_dbuf_mbus_post_ddb_update()
3609 } else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus && in intel_dbuf_mbus_post_ddb_update()
3610 old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) { in intel_dbuf_mbus_post_ddb_update()
3611 WARN_ON(!new_dbuf_state->base.changed); in intel_dbuf_mbus_post_ddb_update()
3621 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dbuf_pre_plane_update()
3631 old_slices = old_dbuf_state->enabled_slices; in intel_dbuf_pre_plane_update()
3632 new_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; in intel_dbuf_pre_plane_update()
3637 WARN_ON(!new_dbuf_state->base.changed); in intel_dbuf_pre_plane_update()
3644 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dbuf_post_plane_update()
3654 old_slices = old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices; in intel_dbuf_post_plane_update()
3655 new_slices = new_dbuf_state->enabled_slices; in intel_dbuf_post_plane_update()
3660 WARN_ON(!new_dbuf_state->base.changed); in intel_dbuf_post_plane_update()
3667 struct intel_display *display = &i915->display; in skl_mbus_sanitize()
3669 to_intel_dbuf_state(display->dbuf.obj.state); in skl_mbus_sanitize()
3674 if (!dbuf_state->joined_mbus || in skl_mbus_sanitize()
3675 adlp_check_mbus_joined(dbuf_state->active_pipes)) in skl_mbus_sanitize()
3678 drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n", in skl_mbus_sanitize()
3679 dbuf_state->active_pipes); in skl_mbus_sanitize()
3681 dbuf_state->joined_mbus = false; in skl_mbus_sanitize()
3683 dbuf_state->mdclk_cdclk_ratio, in skl_mbus_sanitize()
3684 dbuf_state->joined_mbus); in skl_mbus_sanitize()
3692 to_intel_dbuf_state(i915->display.dbuf.obj.state); in skl_dbuf_is_misconfigured()
3696 for_each_intel_crtc(&i915->drm, crtc) { in skl_dbuf_is_misconfigured()
3698 to_intel_crtc_state(crtc->base.state); in skl_dbuf_is_misconfigured()
3700 entries[crtc->pipe] = crtc_state->wm.skl.ddb; in skl_dbuf_is_misconfigured()
3703 for_each_intel_crtc(&i915->drm, crtc) { in skl_dbuf_is_misconfigured()
3705 to_intel_crtc_state(crtc->base.state); in skl_dbuf_is_misconfigured()
3708 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, in skl_dbuf_is_misconfigured()
3709 dbuf_state->joined_mbus); in skl_dbuf_is_misconfigured()
3710 if (dbuf_state->slices[crtc->pipe] & ~slices) in skl_dbuf_is_misconfigured()
3713 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, in skl_dbuf_is_misconfigured()
3714 I915_MAX_PIPES, crtc->pipe)) in skl_dbuf_is_misconfigured()
3739 drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); in skl_dbuf_sanitize()
3741 for_each_intel_crtc(&i915->drm, crtc) { in skl_dbuf_sanitize()
3742 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in skl_dbuf_sanitize()
3744 to_intel_plane_state(plane->base.state); in skl_dbuf_sanitize()
3746 to_intel_crtc_state(crtc->base.state); in skl_dbuf_sanitize()
3748 if (plane_state->uapi.visible) in skl_dbuf_sanitize()
3751 drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0); in skl_dbuf_sanitize()
3753 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); in skl_dbuf_sanitize()
3769 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_wm_state_verify()
3779 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; in intel_wm_state_verify()
3784 if (DISPLAY_VER(i915) < 9 || !new_crtc_state->hw.active) in intel_wm_state_verify()
3791 skl_pipe_wm_get_hw_state(crtc, &hw->wm); in intel_wm_state_verify()
3793 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb); in intel_wm_state_verify()
3798 hw_enabled_slices != i915->display.dbuf.enabled_slices) in intel_wm_state_verify()
3799 drm_err(&i915->drm, in intel_wm_state_verify()
3801 i915->display.dbuf.enabled_slices, in intel_wm_state_verify()
3804 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in intel_wm_state_verify()
3809 for (level = 0; level < i915->display.wm.num_levels; level++) { in intel_wm_state_verify()
3810 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; in intel_wm_state_verify()
3811 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); in intel_wm_state_verify()
3816 drm_err(&i915->drm, in intel_wm_state_verify()
3818 plane->base.base.id, plane->base.name, level, in intel_wm_state_verify()
3819 sw_wm_level->enable, in intel_wm_state_verify()
3820 sw_wm_level->blocks, in intel_wm_state_verify()
3821 sw_wm_level->lines, in intel_wm_state_verify()
3822 hw_wm_level->enable, in intel_wm_state_verify()
3823 hw_wm_level->blocks, in intel_wm_state_verify()
3824 hw_wm_level->lines); in intel_wm_state_verify()
3827 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; in intel_wm_state_verify()
3828 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); in intel_wm_state_verify()
3831 drm_err(&i915->drm, in intel_wm_state_verify()
3833 plane->base.base.id, plane->base.name, in intel_wm_state_verify()
3834 sw_wm_level->enable, in intel_wm_state_verify()
3835 sw_wm_level->blocks, in intel_wm_state_verify()
3836 sw_wm_level->lines, in intel_wm_state_verify()
3837 hw_wm_level->enable, in intel_wm_state_verify()
3838 hw_wm_level->blocks, in intel_wm_state_verify()
3839 hw_wm_level->lines); in intel_wm_state_verify()
3842 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; in intel_wm_state_verify()
3843 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; in intel_wm_state_verify()
3847 drm_err(&i915->drm, in intel_wm_state_verify()
3849 plane->base.base.id, plane->base.name, in intel_wm_state_verify()
3850 sw_wm_level->enable, in intel_wm_state_verify()
3851 sw_wm_level->blocks, in intel_wm_state_verify()
3852 sw_wm_level->lines, in intel_wm_state_verify()
3853 hw_wm_level->enable, in intel_wm_state_verify()
3854 hw_wm_level->blocks, in intel_wm_state_verify()
3855 hw_wm_level->lines); in intel_wm_state_verify()
3858 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; in intel_wm_state_verify()
3859 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; in intel_wm_state_verify()
3863 drm_err(&i915->drm, in intel_wm_state_verify()
3865 plane->base.base.id, plane->base.name, in intel_wm_state_verify()
3866 sw_wm_level->enable, in intel_wm_state_verify()
3867 sw_wm_level->blocks, in intel_wm_state_verify()
3868 sw_wm_level->lines, in intel_wm_state_verify()
3869 hw_wm_level->enable, in intel_wm_state_verify()
3870 hw_wm_level->blocks, in intel_wm_state_verify()
3871 hw_wm_level->lines); in intel_wm_state_verify()
3875 hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; in intel_wm_state_verify()
3876 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; in intel_wm_state_verify()
3879 drm_err(&i915->drm, in intel_wm_state_verify()
3881 plane->base.base.id, plane->base.name, in intel_wm_state_verify()
3882 sw_ddb_entry->start, sw_ddb_entry->end, in intel_wm_state_verify()
3883 hw_ddb_entry->start, hw_ddb_entry->end); in intel_wm_state_verify()
3901 i915->display.funcs.wm = &skl_wm_funcs; in skl_wm_init()
3906 struct drm_i915_private *i915 = m->private; in skl_watermark_ipc_status_show()
3915 struct drm_i915_private *i915 = inode->i_private; in skl_watermark_ipc_status_open()
3924 struct seq_file *m = file->private_data; in skl_watermark_ipc_status_write()
3925 struct drm_i915_private *i915 = m->private; in skl_watermark_ipc_status_write()
3934 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { in skl_watermark_ipc_status_write()
3936 drm_info(&i915->drm, in skl_watermark_ipc_status_write()
3938 i915->display.wm.ipc_enabled = enable; in skl_watermark_ipc_status_write()
3956 struct drm_i915_private *i915 = m->private; in intel_sagv_status_show()
3966 str_enabled_disabled(i915->display.params.enable_sagv)); in intel_sagv_status_show()
3967 seq_printf(m, "SAGV status: %s\n", sagv_status[i915->display.sagv.status]); in intel_sagv_status_show()
3968 seq_printf(m, "SAGV block time: %d usec\n", i915->display.sagv.block_time_us); in intel_sagv_status_show()
3977 struct intel_display *display = &i915->display; in skl_watermark_debugfs_register()
3978 struct drm_minor *minor = display->drm->primary; in skl_watermark_debugfs_register()
3981 debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915, in skl_watermark_debugfs_register()
3985 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915, in skl_watermark_debugfs_register()
3993 for (level = i915->display.wm.num_levels - 1; level >= initial_wm_level; level--) { in skl_watermark_max_latency()