Lines Matching full:display
23 static void vlv_steal_power_sequencer(struct intel_display *display,
31 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
67 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
68 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_lock()
75 mutex_lock(&display->pps.mutex); in intel_pps_lock()
83 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
84 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_unlock()
86 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
95 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
96 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_power_sequencer_kick()
104 if (drm_WARN(display->drm, in vlv_power_sequencer_kick()
105 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
111 drm_dbg_kms(display->drm, in vlv_power_sequencer_kick()
119 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
124 if (display->platform.cherryview) in vlv_power_sequencer_kick()
129 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
136 release_cl_override = display->platform.cherryview && in vlv_power_sequencer_kick()
137 !chv_phy_powergate_ch(display, phy, ch, true); in vlv_power_sequencer_kick()
140 drm_err(display->drm, in vlv_power_sequencer_kick()
153 intel_de_write(display, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
154 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
156 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
157 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
159 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
160 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
166 chv_phy_powergate_ch(display, phy, ch, false); in vlv_power_sequencer_kick()
170 static enum pipe vlv_find_free_pps(struct intel_display *display) in vlv_find_free_pps() argument
179 for_each_intel_dp(display->drm, encoder) { in vlv_find_free_pps()
183 drm_WARN_ON(display->drm, in vlv_find_free_pps()
191 drm_WARN_ON(display->drm, in vlv_find_free_pps()
208 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_pipe() local
212 lockdep_assert_held(&display->pps.mutex); in vlv_power_sequencer_pipe()
215 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in vlv_power_sequencer_pipe()
217 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
223 pipe = vlv_find_free_pps(display); in vlv_power_sequencer_pipe()
229 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE)) in vlv_power_sequencer_pipe()
232 vlv_steal_power_sequencer(display, pipe); in vlv_power_sequencer_pipe()
235 drm_dbg_kms(display->drm, in vlv_power_sequencer_pipe()
256 struct intel_display *display = to_intel_display(intel_dp); in bxt_power_sequencer_idx() local
259 lockdep_assert_held(&display->pps.mutex); in bxt_power_sequencer_idx()
262 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in bxt_power_sequencer_idx()
278 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
280 static bool pps_has_pp_on(struct intel_display *display, int pps_idx) in pps_has_pp_on() argument
282 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON; in pps_has_pp_on()
285 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx) in pps_has_vdd_on() argument
287 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on()
290 static bool pps_any(struct intel_display *display, int pps_idx) in pps_any() argument
296 vlv_initial_pps_pipe(struct intel_display *display, in vlv_initial_pps_pipe() argument
302 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe()
303 PP_ON_DELAYS(display, pipe)) & in vlv_initial_pps_pipe()
309 if (!check(display, pipe)) in vlv_initial_pps_pipe()
321 struct intel_display *display = to_intel_display(intel_dp); in vlv_initial_power_sequencer_setup() local
325 lockdep_assert_held(&display->pps.mutex); in vlv_initial_power_sequencer_setup()
329 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
333 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
337 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
342 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
348 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
354 static int intel_num_pps(struct intel_display *display) in intel_num_pps() argument
356 struct drm_i915_private *i915 = to_i915(display->drm); in intel_num_pps()
358 if (display->platform.valleyview || display->platform.cherryview) in intel_num_pps()
361 if (display->platform.geminilake || display->platform.broxton) in intel_num_pps()
378 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_is_valid() local
379 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_is_valid()
384 return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; in intel_pps_is_valid()
390 bxt_initial_pps_idx(struct intel_display *display, pps_check check) in bxt_initial_pps_idx() argument
392 int pps_idx, pps_num = intel_num_pps(display); in bxt_initial_pps_idx()
395 if (check(display, pps_idx)) in bxt_initial_pps_idx()
405 struct intel_display *display = to_intel_display(intel_dp); in pps_initial_setup() local
409 lockdep_assert_held(&display->pps.mutex); in pps_initial_setup()
411 if (display->platform.valleyview || display->platform.cherryview) { in pps_initial_setup()
417 if (intel_num_pps(display) > 1) in pps_initial_setup()
422 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display))) in pps_initial_setup()
427 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on); in pps_initial_setup()
430 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on); in pps_initial_setup()
433 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any); in pps_initial_setup()
435 drm_dbg_kms(display->drm, in pps_initial_setup()
440 drm_dbg_kms(display->drm, in pps_initial_setup()
449 void vlv_pps_reset_all(struct intel_display *display) in vlv_pps_reset_all() argument
453 if (!HAS_DISPLAY(display)) in vlv_pps_reset_all()
466 for_each_intel_dp(display->drm, encoder) { in vlv_pps_reset_all()
469 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_reset_all()
476 void bxt_pps_reset_all(struct intel_display *display) in bxt_pps_reset_all() argument
480 if (!HAS_DISPLAY(display)) in bxt_pps_reset_all()
485 for_each_intel_dp(display->drm, encoder) { in bxt_pps_reset_all()
504 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_get_registers() local
505 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_get_registers()
510 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_get_registers()
512 else if (display->platform.geminilake || display->platform.broxton) in intel_pps_get_registers()
517 regs->pp_ctrl = PP_CONTROL(display, pps_idx); in intel_pps_get_registers()
518 regs->pp_stat = PP_STATUS(display, pps_idx); in intel_pps_get_registers()
519 regs->pp_on = PP_ON_DELAYS(display, pps_idx); in intel_pps_get_registers()
520 regs->pp_off = PP_OFF_DELAYS(display, pps_idx); in intel_pps_get_registers()
523 if (display->platform.geminilake || display->platform.broxton || in intel_pps_get_registers()
527 regs->pp_div = PP_DIVISOR(display, pps_idx); in intel_pps_get_registers()
552 struct intel_display *display = to_intel_display(intel_dp); in edp_have_panel_power() local
554 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_power()
556 if ((display->platform.valleyview || display->platform.cherryview) && in edp_have_panel_power()
560 return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
565 struct intel_display *display = to_intel_display(intel_dp); in edp_have_panel_vdd() local
567 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_vdd()
569 if ((display->platform.valleyview || display->platform.cherryview) && in edp_have_panel_vdd()
573 return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
578 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_check_power_unlocked() local
585 drm_WARN(display->drm, 1, in intel_pps_check_power_unlocked()
589 drm_dbg_kms(display->drm, in intel_pps_check_power_unlocked()
593 intel_de_read(display, _pp_stat_reg(intel_dp)), in intel_pps_check_power_unlocked()
594 intel_de_read(display, _pp_ctrl_reg(intel_dp))); in intel_pps_check_power_unlocked()
612 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_status() local
616 lockdep_assert_held(&display->pps.mutex); in wait_panel_status()
623 drm_dbg_kms(display->drm, in wait_panel_status()
628 intel_de_read(display, pp_stat_reg), in wait_panel_status()
629 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
631 if (intel_de_wait(display, pp_stat_reg, mask, value, 5000)) in wait_panel_status()
632 drm_err(display->drm, in wait_panel_status()
636 intel_de_read(display, pp_stat_reg), in wait_panel_status()
637 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
639 drm_dbg_kms(display->drm, "Wait complete\n"); in wait_panel_status()
644 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_on() local
647 drm_dbg_kms(display->drm, in wait_panel_on()
656 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_off() local
659 drm_dbg_kms(display->drm, in wait_panel_off()
668 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_power_cycle() local
680 drm_dbg_kms(display->drm, in wait_panel_power_cycle()
722 struct intel_display *display = to_intel_display(intel_dp); in ilk_get_pp_control() local
725 lockdep_assert_held(&display->pps.mutex); in ilk_get_pp_control()
727 control = intel_de_read(display, _pp_ctrl_reg(intel_dp)); in ilk_get_pp_control()
728 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
743 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_on_unlocked() local
744 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_vdd_on_unlocked()
750 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_on_unlocked()
761 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
768 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n", in intel_pps_vdd_on_unlocked()
778 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
779 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
780 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
784 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_on_unlocked()
785 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
790 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
809 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_on() local
819 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", in intel_pps_vdd_on()
827 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_off_sync_unlocked() local
828 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_vdd_off_sync_unlocked()
833 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_sync_unlocked()
835 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
840 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n", in intel_pps_vdd_off_sync_unlocked()
850 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
851 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
854 drm_dbg_kms(display->drm, in intel_pps_vdd_off_sync_unlocked()
858 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
859 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_off_sync_unlocked()
902 struct intel_display *display = to_intel_display(intel_dp); in edp_panel_vdd_schedule_off() local
903 struct drm_i915_private *i915 = to_i915(display->drm); in edp_panel_vdd_schedule_off()
930 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_off_unlocked() local
932 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_unlocked()
937 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd, in intel_pps_vdd_off_unlocked()
964 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_on_unlocked() local
968 lockdep_assert_held(&display->pps.mutex); in intel_pps_on_unlocked()
973 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n", in intel_pps_on_unlocked()
978 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp), in intel_pps_on_unlocked()
989 if (display->platform.ironlake) { in intel_pps_on_unlocked()
992 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
993 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1000 if (IS_DISPLAY_VER(display, 13, 14)) in intel_pps_on_unlocked()
1001 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in intel_pps_on_unlocked()
1005 if (!display->platform.ironlake) in intel_pps_on_unlocked()
1008 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1009 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1014 if (IS_DISPLAY_VER(display, 13, 14)) in intel_pps_on_unlocked()
1015 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in intel_pps_on_unlocked()
1018 if (display->platform.ironlake) { in intel_pps_on_unlocked()
1020 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1021 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1038 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_off_unlocked() local
1039 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_off_unlocked()
1044 lockdep_assert_held(&display->pps.mutex); in intel_pps_off_unlocked()
1049 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n", in intel_pps_off_unlocked()
1053 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
1068 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
1069 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_off_unlocked()
1096 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_backlight_on() local
1114 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_on()
1115 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_on()
1122 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_backlight_off() local
1135 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_off()
1136 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_off()
1149 struct intel_display *display = to_intel_display(connector); in intel_pps_backlight_power() local
1160 drm_dbg_kms(display->drm, "panel power control backlight %s\n", in intel_pps_backlight_power()
1171 struct intel_display *display = to_intel_display(intel_dp); in vlv_detach_power_sequencer() local
1174 i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); in vlv_detach_power_sequencer()
1176 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
1178 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1192 drm_dbg_kms(display->drm, in vlv_detach_power_sequencer()
1196 intel_de_write(display, pp_on_reg, 0); in vlv_detach_power_sequencer()
1197 intel_de_posting_read(display, pp_on_reg); in vlv_detach_power_sequencer()
1202 static void vlv_steal_power_sequencer(struct intel_display *display, in vlv_steal_power_sequencer() argument
1207 lockdep_assert_held(&display->pps.mutex); in vlv_steal_power_sequencer()
1209 for_each_intel_dp(display->drm, encoder) { in vlv_steal_power_sequencer()
1212 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe, in vlv_steal_power_sequencer()
1220 drm_dbg_kms(display->drm, in vlv_steal_power_sequencer()
1232 struct intel_display *display = to_intel_display(intel_dp); in vlv_active_pipe() local
1233 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_active_pipe()
1284 struct intel_display *display = to_intel_display(encoder); in vlv_pps_port_enable_unlocked() local
1288 lockdep_assert_held(&display->pps.mutex); in vlv_pps_port_enable_unlocked()
1290 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_port_enable_unlocked()
1306 vlv_steal_power_sequencer(display, crtc->pipe); in vlv_pps_port_enable_unlocked()
1316 drm_dbg_kms(display->drm, in vlv_pps_port_enable_unlocked()
1340 struct intel_display *display = to_intel_display(intel_dp); in pps_vdd_init() local
1341 struct drm_i915_private *dev_priv = to_i915(display->drm); in pps_vdd_init()
1344 lockdep_assert_held(&display->pps.mutex); in pps_vdd_init()
1355 drm_dbg_kms(display->drm, in pps_vdd_init()
1359 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in pps_vdd_init()
1393 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_readout_hw_state() local
1402 if (!HAS_DDI(display)) in intel_pps_readout_hw_state()
1403 intel_de_write(display, regs.pp_ctrl, pp_ctl); in intel_pps_readout_hw_state()
1405 pp_on = intel_de_read(display, regs.pp_on); in intel_pps_readout_hw_state()
1406 pp_off = intel_de_read(display, regs.pp_off); in intel_pps_readout_hw_state()
1417 pp_div = intel_de_read(display, regs.pp_div); in intel_pps_readout_hw_state()
1432 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_dump_state() local
1434 drm_dbg_kms(display->drm, in intel_pps_dump_state()
1443 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_verify_state() local
1454 drm_err(display->drm, "PPS state mismatch\n"); in intel_pps_verify_state()
1481 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_bios() local
1483 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_bios()
1496 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_vbt() local
1509 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) { in pps_init_delays_vbt()
1511 drm_dbg_kms(display->drm, in pps_init_delays_vbt()
1522 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_spec() local
1524 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_spec()
1538 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays() local
1542 lockdep_assert_held(&display->pps.mutex); in pps_init_delays()
1570 drm_dbg_kms(display->drm, in pps_init_delays()
1576 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n", in pps_init_delays()
1600 struct intel_display *display = to_intel_display(intel_dp); in pps_init_registers() local
1601 struct drm_i915_private *dev_priv = to_i915(display->drm); in pps_init_registers()
1603 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; in pps_init_registers()
1608 lockdep_assert_held(&display->pps.mutex); in pps_init_registers()
1627 drm_WARN(display->drm, pp & PANEL_POWER_ON, in pps_init_registers()
1631 drm_dbg_kms(display->drm, in pps_init_registers()
1636 intel_de_write(display, regs.pp_ctrl, pp); in pps_init_registers()
1646 if (display->platform.valleyview || display->platform.cherryview) { in pps_init_registers()
1667 intel_de_write(display, regs.pp_on, pp_on); in pps_init_registers()
1668 intel_de_write(display, regs.pp_off, pp_off); in pps_init_registers()
1674 intel_de_write(display, regs.pp_div, in pps_init_registers()
1680 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK, in pps_init_registers()
1684 drm_dbg_kms(display->drm, in pps_init_registers()
1686 intel_de_read(display, regs.pp_on), in pps_init_registers()
1687 intel_de_read(display, regs.pp_off), in pps_init_registers()
1689 intel_de_read(display, regs.pp_div) : in pps_init_registers()
1690 (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); in pps_init_registers()
1695 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_encoder_reset() local
1706 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_encoder_reset()
1741 struct intel_display *display = to_intel_display(intel_dp); in pps_init_late() local
1745 if (display->platform.valleyview || display->platform.cherryview) in pps_init_late()
1748 if (intel_num_pps(display) < 2) in pps_init_late()
1751 drm_WARN(display->drm, in pps_init_late()
1781 void intel_pps_unlock_regs_wa(struct intel_display *display) in intel_pps_unlock_regs_wa() argument
1786 if (!HAS_DISPLAY(display) || HAS_DDI(display)) in intel_pps_unlock_regs_wa()
1792 pps_num = intel_num_pps(display); in intel_pps_unlock_regs_wa()
1795 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa()
1799 void intel_pps_setup(struct intel_display *display) in intel_pps_setup() argument
1801 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_setup()
1803 if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton) in intel_pps_setup()
1804 display->pps.mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1805 else if (display->platform.valleyview || display->platform.cherryview) in intel_pps_setup()
1806 display->pps.mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1808 display->pps.mmio_base = PPS_BASE; in intel_pps_setup()
1844 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) in assert_pps_unlocked() argument
1846 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_pps_unlocked()
1852 if (drm_WARN_ON(display->drm, HAS_DDI(display))) in assert_pps_unlocked()
1858 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
1859 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
1879 } else if (display->platform.valleyview || display->platform.cherryview) { in assert_pps_unlocked()
1881 pp_reg = PP_CONTROL(display, pipe); in assert_pps_unlocked()
1886 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
1887 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
1890 drm_WARN_ON(display->drm, in assert_pps_unlocked()
1895 val = intel_de_read(display, pp_reg); in assert_pps_unlocked()
1900 INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked, in assert_pps_unlocked()