2  * Copyright © 2006-2007 Intel Corporation
58 /* Private structure for the integrated LVDS support */
81 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)  in to_lvds_encoder()  argument
83 	return container_of(encoder, struct intel_lvds_encoder, base);  in to_lvds_encoder()
102 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,  in intel_lvds_get_hw_state()  argument
105 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_lvds_get_hw_state()
106 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);  in intel_lvds_get_hw_state()
110 	wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);  in intel_lvds_get_hw_state()
114 	ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);  in intel_lvds_get_hw_state()
116 	intel_display_power_put(i915, encoder->power_domain, wakeref);  in intel_lvds_get_hw_state()
121 static void intel_lvds_get_config(struct intel_encoder *encoder,  in intel_lvds_get_config()  argument
124 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_lvds_get_config()
125 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);  in intel_lvds_get_config()
128 	crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);  in intel_lvds_get_config()
130 	tmp = intel_de_read(dev_priv, lvds_encoder->reg);  in intel_lvds_get_config()
140 	crtc_state->hw.adjusted_mode.flags |= flags;  in intel_lvds_get_config()
143 		crtc_state->gmch_pfit.lvds_border_bits =  in intel_lvds_get_config()
150 		crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;  in intel_lvds_get_config()
153 	crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;  in intel_lvds_get_config()
161 	pps->powerdown_on_reset = intel_de_read(dev_priv,  in intel_lvds_pps_get_hw_state()
165 	pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);  in intel_lvds_pps_get_hw_state()
166 	pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
167 	pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
170 	pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
171 	pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
174 	pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);  in intel_lvds_pps_get_hw_state()
178 	 * too short power-cycle delay due to the asynchronous programming of  in intel_lvds_pps_get_hw_state()
182 		val--;  in intel_lvds_pps_get_hw_state()
184 	pps->delays.power_cycle = val * 1000;  in intel_lvds_pps_get_hw_state()
187 	    pps->delays.power_up == 0 &&  in intel_lvds_pps_get_hw_state()
188 	    pps->delays.backlight_on == 0 &&  in intel_lvds_pps_get_hw_state()
189 	    pps->delays.power_down == 0 &&  in intel_lvds_pps_get_hw_state()
190 	    pps->delays.backlight_off == 0) {  in intel_lvds_pps_get_hw_state()
191 		drm_dbg_kms(&dev_priv->drm,  in intel_lvds_pps_get_hw_state()
195 		pps->delays.power_up = 40 * 10;  in intel_lvds_pps_get_hw_state()
196 		pps->delays.backlight_on = 200 * 10;  in intel_lvds_pps_get_hw_state()
198 		pps->delays.power_down = 35 * 10;  in intel_lvds_pps_get_hw_state()
199 		pps->delays.backlight_off = 200 * 10;  in intel_lvds_pps_get_hw_state()
202 …drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlig…  in intel_lvds_pps_get_hw_state()
204 		pps->delays.power_up, pps->delays.power_down,  in intel_lvds_pps_get_hw_state()
205 		pps->delays.power_cycle, pps->delays.backlight_on,  in intel_lvds_pps_get_hw_state()
206 		pps->delays.backlight_off, pps->divider,  in intel_lvds_pps_get_hw_state()
207 		pps->port, pps->powerdown_on_reset);  in intel_lvds_pps_get_hw_state()
216 	drm_WARN_ON(&dev_priv->drm,  in intel_lvds_pps_init_hw()
218 	if (pps->powerdown_on_reset)  in intel_lvds_pps_init_hw()
223 		       REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |  in intel_lvds_pps_init_hw()
224 		       REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |  in intel_lvds_pps_init_hw()
225 		       REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));  in intel_lvds_pps_init_hw()
228 		       REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |  in intel_lvds_pps_init_hw()
229 		       REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));  in intel_lvds_pps_init_hw()
232 		       REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |  in intel_lvds_pps_init_hw()
234 				      DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));  in intel_lvds_pps_init_hw()
238 				  struct intel_encoder *encoder,  in intel_pre_enable_lvds()  argument
242 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);  in intel_pre_enable_lvds()
243 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_pre_enable_lvds()
244 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_pre_enable_lvds()
245 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_pre_enable_lvds()
246 	enum pipe pipe = crtc->pipe;  in intel_pre_enable_lvds()
251 		assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);  in intel_pre_enable_lvds()
256 	intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);  in intel_pre_enable_lvds()
258 	temp = lvds_encoder->init_lvds_val;  in intel_pre_enable_lvds()
271 	temp |= crtc_state->gmch_pfit.lvds_border_bits;  in intel_pre_enable_lvds()
274 	 * Set the B0-B3 data pairs corresponding to whether we're going to  in intel_pre_enable_lvds()
275 	 * set the DPLLs for dual-channel mode or not.  in intel_pre_enable_lvds()
277 	if (lvds_encoder->is_dual_link)  in intel_pre_enable_lvds()
283 	 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)  in intel_pre_enable_lvds()
289 	temp |= lvds_encoder->a3_power;  in intel_pre_enable_lvds()
292 	 * Set the dithering flag on LVDS as needed, note that there is no  in intel_pre_enable_lvds()
293 	 * special lvds dither control bit on pch-split platforms, dithering is  in intel_pre_enable_lvds()
298 		 * Bspec wording suggests that LVDS port dithering only exists  in intel_pre_enable_lvds()
301 		if (crtc_state->dither && crtc_state->pipe_bpp == 18)  in intel_pre_enable_lvds()
307 	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)  in intel_pre_enable_lvds()
309 	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)  in intel_pre_enable_lvds()
312 	intel_de_write(i915, lvds_encoder->reg, temp);  in intel_pre_enable_lvds()
319 			      struct intel_encoder *encoder,  in intel_enable_lvds()  argument
323 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);  in intel_enable_lvds()
324 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_enable_lvds()
326 	intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);  in intel_enable_lvds()
329 	intel_de_posting_read(dev_priv, lvds_encoder->reg);  in intel_enable_lvds()
332 		drm_err(&dev_priv->drm,  in intel_enable_lvds()
339 			       struct intel_encoder *encoder,  in intel_disable_lvds()  argument
343 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);  in intel_disable_lvds()
344 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_disable_lvds()
348 		drm_err(&dev_priv->drm,  in intel_disable_lvds()
351 	intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);  in intel_disable_lvds()
352 	intel_de_posting_read(dev_priv, lvds_encoder->reg);  in intel_disable_lvds()
356 			      struct intel_encoder *encoder,  in gmch_disable_lvds()  argument
363 	intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);  in gmch_disable_lvds()
367 			     struct intel_encoder *encoder,  in pch_disable_lvds()  argument
375 				  struct intel_encoder *encoder,  in pch_post_disable_lvds()  argument
379 	intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);  in pch_post_disable_lvds()
382 static void intel_lvds_shutdown(struct intel_encoder *encoder)  in intel_lvds_shutdown()  argument
384 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_lvds_shutdown()
387 		drm_err(&dev_priv->drm,  in intel_lvds_shutdown()
396 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_lvds_mode_valid()
399 	int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq;  in intel_lvds_mode_valid()
410 	if (fixed_mode->clock > max_pixclk)  in intel_lvds_mode_valid()
416 static int intel_lvds_compute_config(struct intel_encoder *encoder,  in intel_lvds_compute_config()  argument
420 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_lvds_compute_config()
421 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);  in intel_lvds_compute_config()
422 	struct intel_connector *connector = lvds_encoder->attached_connector;  in intel_lvds_compute_config()
423 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_lvds_compute_config()
424 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_lvds_compute_config()
429 	if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {  in intel_lvds_compute_config()
430 		drm_err(&i915->drm, "Can't support LVDS on pipe A\n");  in intel_lvds_compute_config()
431 		return -EINVAL;  in intel_lvds_compute_config()
435 		crtc_state->has_pch_encoder = true;  in intel_lvds_compute_config()
437 			return -EINVAL;  in intel_lvds_compute_config()
440 	if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)  in intel_lvds_compute_config()
445 	/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */  in intel_lvds_compute_config()
446 	if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {  in intel_lvds_compute_config()
447 		drm_dbg_kms(&i915->drm,  in intel_lvds_compute_config()
448 			    "forcing display bpp (was %d) to LVDS (%d)\n",  in intel_lvds_compute_config()
449 			    crtc_state->pipe_bpp, lvds_bpp);  in intel_lvds_compute_config()
450 		crtc_state->pipe_bpp = lvds_bpp;  in intel_lvds_compute_config()
453 	crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_lvds_compute_config()
454 	crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_lvds_compute_config()
466 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)  in intel_lvds_compute_config()
467 		return -EINVAL;  in intel_lvds_compute_config()
488 	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;  in intel_lvds_get_modes()
492 		drm_edid_connector_update(&connector->base, fixed_edid);  in intel_lvds_get_modes()
494 		return drm_edid_connector_add_modes(&connector->base);  in intel_lvds_get_modes()
524 	DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);  in intel_no_lvds_dmi_callback()
528 /* These systems claim to have LVDS, but really don't */
548 		.ident = "MSI IM-945GSE-A",
575 			DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
583 			DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
588 		.ident = "AOpen i915GMm-HFS",
591 			DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
596 		.ident = "AOpen i45GMx-I",
599 			DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
604 		.ident = "Aopen i945GTt-VFA",
635 		.ident = "Asus AT5NM10T-I",
638 			DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
643 		.ident = "Hewlett-Packard HP t5740",
645 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
651 		.ident = "Hewlett-Packard t5745",
653 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
659 		.ident = "Hewlett-Packard st5747",
661 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
669 			DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
670 			DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
675 		.ident = "Gigabyte GA-D525TUD",
683 		.ident = "Supermicro X7SPA-H",
686 			DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
743 	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);  in intel_dual_link_lvds_callback()
777 	struct intel_encoder *encoder;  in intel_get_lvds_encoder()  local
779 	for_each_intel_encoder(&i915->drm, encoder) {  in intel_get_lvds_encoder()
780 		if (encoder->type == INTEL_OUTPUT_LVDS)  in intel_get_lvds_encoder()
781 			return encoder;  in intel_get_lvds_encoder()
789 	struct intel_encoder *encoder = intel_get_lvds_encoder(i915);  in intel_is_dual_link_lvds()  local
791 	return encoder && to_lvds_encoder(encoder)->is_dual_link;  in intel_is_dual_link_lvds()
796 	struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);  in compute_is_dual_link_lvds()
797 	struct intel_connector *connector = lvds_encoder->attached_connector;  in compute_is_dual_link_lvds()
803 	if (i915->display.params.lvds_channel_mode > 0)  in compute_is_dual_link_lvds()
804 		return i915->display.params.lvds_channel_mode == 2;  in compute_is_dual_link_lvds()
806 	/* single channel LVDS is limited to 112 MHz */  in compute_is_dual_link_lvds()
807 	if (fixed_mode->clock > 112999)  in compute_is_dual_link_lvds()
814 	 * BIOS should set the proper LVDS register value at boot, but  in compute_is_dual_link_lvds()
816 	 * we need to check "the value to be set" in VBT when LVDS  in compute_is_dual_link_lvds()
819 	val = intel_de_read(i915, lvds_encoder->reg);  in compute_is_dual_link_lvds()
825 		val = connector->panel.vbt.bios_lvds_val;  in compute_is_dual_link_lvds()
836  * intel_lvds_init - setup LVDS connectors on this device
839  * Create the connector, register the LVDS DDC bus, and try to figure out what
840  * modes we can display on the LVDS panel (if present).
844 	struct intel_display *display = &i915->display;  in intel_lvds_init()
848 	struct intel_encoder *encoder;  in intel_lvds_init()  local
850 	u32 lvds;  in intel_lvds_init()  local
853 	/* Skip init on machines we know falsely report LVDS */  in intel_lvds_init()
855 		drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,  in intel_lvds_init()
856 			 "Useless DMI match. Internal LVDS support disabled by VBT\n");  in intel_lvds_init()
860 	if (!i915->display.vbt.int_lvds_support) {  in intel_lvds_init()
861 		drm_dbg_kms(&i915->drm,  in intel_lvds_init()
862 			    "Internal LVDS support disabled by VBT\n");  in intel_lvds_init()
869 		lvds_reg = LVDS;  in intel_lvds_init()
871 	lvds = intel_de_read(i915, lvds_reg);  in intel_lvds_init()
874 		if ((lvds & LVDS_DETECTED) == 0)  in intel_lvds_init()
880 		if ((lvds & LVDS_PORT_EN) == 0) {  in intel_lvds_init()
881 			drm_dbg_kms(&i915->drm,  in intel_lvds_init()
882 				    "LVDS is not present in VBT\n");  in intel_lvds_init()
885 		drm_dbg_kms(&i915->drm,  in intel_lvds_init()
886 			    "LVDS is not present in VBT, but enabled anyway\n");  in intel_lvds_init()
899 	lvds_encoder->attached_connector = connector;  in intel_lvds_init()
900 	encoder = &lvds_encoder->base;  in intel_lvds_init()
902 	drm_connector_init_with_ddc(&i915->drm, &connector->base,  in intel_lvds_init()
907 	drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,  in intel_lvds_init()
908 			 DRM_MODE_ENCODER_LVDS, "LVDS");  in intel_lvds_init()
910 	encoder->enable = intel_enable_lvds;  in intel_lvds_init()
911 	encoder->pre_enable = intel_pre_enable_lvds;  in intel_lvds_init()
912 	encoder->compute_config = intel_lvds_compute_config;  in intel_lvds_init()
914 		encoder->disable = pch_disable_lvds;  in intel_lvds_init()
915 		encoder->post_disable = pch_post_disable_lvds;  in intel_lvds_init()
917 		encoder->disable = gmch_disable_lvds;  in intel_lvds_init()
919 	encoder->get_hw_state = intel_lvds_get_hw_state;  in intel_lvds_init()
920 	encoder->get_config = intel_lvds_get_config;  in intel_lvds_init()
921 	encoder->update_pipe = intel_backlight_update;  in intel_lvds_init()
922 	encoder->shutdown = intel_lvds_shutdown;  in intel_lvds_init()
923 	connector->get_hw_state = intel_connector_get_hw_state;  in intel_lvds_init()
925 	intel_connector_attach_encoder(connector, encoder);  in intel_lvds_init()
927 	encoder->type = INTEL_OUTPUT_LVDS;  in intel_lvds_init()
928 	encoder->power_domain = POWER_DOMAIN_PORT_OTHER;  in intel_lvds_init()
929 	encoder->port = PORT_NONE;  in intel_lvds_init()
930 	encoder->cloneable = 0;  in intel_lvds_init()
932 		encoder->pipe_mask = BIT(PIPE_B);  in intel_lvds_init()
934 		encoder->pipe_mask = ~0;  in intel_lvds_init()
936 	drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);  in intel_lvds_init()
937 	connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;  in intel_lvds_init()
939 	lvds_encoder->reg = lvds_reg;  in intel_lvds_init()
941 	intel_lvds_add_properties(&connector->base);  in intel_lvds_init()
943 	intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);  in intel_lvds_init()
944 	lvds_encoder->init_lvds_val = lvds;  in intel_lvds_init()
947 	 * LVDS discovery:  in intel_lvds_init()
950 	 * 3) check to see if LVDS is already on  in intel_lvds_init()
958 	mutex_lock(&i915->drm.mode_config.mutex);  in intel_lvds_init()
960 		drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);  in intel_lvds_init()
962 		drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);  in intel_lvds_init()
964 		if (drm_edid_connector_update(&connector->base, drm_edid) ||  in intel_lvds_init()
965 		    !drm_edid_connector_add_modes(&connector->base)) {  in intel_lvds_init()
966 			drm_edid_connector_update(&connector->base, NULL);  in intel_lvds_init()
968 			drm_edid = ERR_PTR(-EINVAL);  in intel_lvds_init()
971 		drm_edid = ERR_PTR(-ENOENT);  in intel_lvds_init()
973 	intel_bios_init_panel_late(display, &connector->panel, NULL,  in intel_lvds_init()
989 		intel_panel_add_encoder_fixed_mode(connector, encoder);  in intel_lvds_init()
991 	mutex_unlock(&i915->drm.mode_config.mutex);  in intel_lvds_init()
1001 	lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);  in intel_lvds_init()
1002 	drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",  in intel_lvds_init()
1003 		    lvds_encoder->is_dual_link ? "dual" : "single");  in intel_lvds_init()
1005 	lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;  in intel_lvds_init()
1010 	drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");  in intel_lvds_init()
1011 	drm_connector_cleanup(&connector->base);  in intel_lvds_init()
1012 	drm_encoder_cleanup(&encoder->base);  in intel_lvds_init()