47  * occurrence until the next modeset on a given pipe.
50  * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
63 	enum pipe pipe;  in ivb_can_enable_err_int()  local
67 	for_each_pipe(dev_priv, pipe) {  in ivb_can_enable_err_int()
68 		crtc = intel_crtc_for_pipe(display, pipe);  in ivb_can_enable_err_int()
81 	enum pipe pipe;  in cpt_can_enable_serr_int()  local
86 	for_each_pipe(dev_priv, pipe) {  in cpt_can_enable_serr_int()
87 		crtc = intel_crtc_for_pipe(display, pipe);  in cpt_can_enable_serr_int()
100 	i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
108 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
112 	trace_intel_cpu_fifo_underrun(display, crtc->pipe);  in i9xx_check_fifo_underruns()
113 	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
117 					     enum pipe pipe,  in i9xx_set_fifo_underrun_reporting()  argument
121 	i915_reg_t reg = PIPESTAT(dev_priv, pipe);  in i9xx_set_fifo_underrun_reporting()
126 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i9xx_set_fifo_underrun_reporting()
133 			drm_err(&dev_priv->drm, "pipe %c underrun\n",  in i9xx_set_fifo_underrun_reporting()
134 				pipe_name(pipe));  in i9xx_set_fifo_underrun_reporting()
139 					    enum pipe pipe, bool enable)  in ilk_set_fifo_underrun_reporting()  argument
142 	u32 bit = (pipe == PIPE_A) ?  in ilk_set_fifo_underrun_reporting()
155 	enum pipe pipe = crtc->pipe;  in ivb_check_fifo_underruns()  local
160 	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)  in ivb_check_fifo_underruns()
163 	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_check_fifo_underruns()
166 	trace_intel_cpu_fifo_underrun(display, pipe);  in ivb_check_fifo_underruns()
167 	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));  in ivb_check_fifo_underruns()
171 					    enum pipe pipe, bool enable,  in ivb_set_fifo_underrun_reporting()  argument
177 			       ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_set_fifo_underrun_reporting()
187 		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {  in ivb_set_fifo_underrun_reporting()
189 				"uncleared fifo underrun on pipe %c\n",  in ivb_set_fifo_underrun_reporting()
190 				pipe_name(pipe));  in ivb_set_fifo_underrun_reporting()
196 					    enum pipe pipe, bool enable)  in bdw_set_fifo_underrun_reporting()  argument
201 		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in bdw_set_fifo_underrun_reporting()
203 		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in bdw_set_fifo_underrun_reporting()
207 					    enum pipe pch_transcoder,  in ibx_set_fifo_underrun_reporting()
224 	enum pipe pch_transcoder = crtc->pipe;  in cpt_check_pch_fifo_underruns()
242 					    enum pipe pch_transcoder,  in cpt_set_fifo_underrun_reporting()
268 						    enum pipe pipe, bool enable)  in __intel_set_cpu_fifo_underrun_reporting()  argument
272 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);  in __intel_set_cpu_fifo_underrun_reporting()
281 		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
283 		ilk_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
285 		ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
287 		bdw_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
295  * @pipe: (CPU) pipe to set state for
298  * This function sets the fifo underrun state for @pipe. It is used in the
300  * expected when disabling or enabling the pipe.
302  * Notice that on some platforms disabling underrun reports for one pipe
303  * disables for all due to shared interrupts. Actual reporting is still per-pipe
309 					   enum pipe pipe, bool enable)  in intel_set_cpu_fifo_underrun_reporting()  argument
315 	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,  in intel_set_cpu_fifo_underrun_reporting()
325  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
337 					   enum pipe pch_transcoder,  in intel_set_pch_fifo_underrun_reporting()
347 	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT  in intel_set_pch_fifo_underrun_reporting()
349 	 * pch transcoder -> pipe lookups from interrupt code simply store the  in intel_set_pch_fifo_underrun_reporting()
376  * @pipe: (CPU) pipe to set state for
383 					 enum pipe pipe)  in intel_cpu_fifo_underrun_irq_handler()  argument
386 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);  in intel_cpu_fifo_underrun_irq_handler()
397 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {  in intel_cpu_fifo_underrun_irq_handler()
398 		trace_intel_cpu_fifo_underrun(display, pipe);  in intel_cpu_fifo_underrun_irq_handler()
400 		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()
409  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
416 					 enum pipe pch_transcoder)  in intel_pch_fifo_underrun_irq_handler()
489 	 * within the crtc. With crtc for pipe A housing the underrun  in intel_init_fifo_underrun_reporting()
490 	 * reporting state for PCH transcoder A, crtc for pipe B housing  in intel_init_fifo_underrun_reporting()
496 	if (intel_has_pch_trancoder(i915, crtc->pipe))  in intel_init_fifo_underrun_reporting()