Lines Matching full:dsb
42 * Previously emitted DSB instruction. Used to
49 * Start of the previously emitted DSB instruction.
60 * DOC: DSB
62 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
63 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
64 * engine that can be programmed to download the DSB from memory.
67 * faster. DSB Support added from Gen12 Intel graphics based platform.
69 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
72 * DSB HW can support only register writes (both indexed and direct MMIO
73 * writes). There are no registers reads possible with DSB HW engine.
76 /* DSB opcodes. */
189 static bool assert_dsb_has_room(struct intel_dsb *dsb) in assert_dsb_has_room() argument
191 struct intel_crtc *crtc = dsb->crtc; in assert_dsb_has_room()
195 return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2, in assert_dsb_has_room()
196 "[CRTC:%d:%s] DSB %d buffer overflow\n", in assert_dsb_has_room()
197 crtc->base.base.id, crtc->base.name, dsb->id); in assert_dsb_has_room()
200 static void intel_dsb_dump(struct intel_dsb *dsb) in intel_dsb_dump() argument
202 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_dump()
206 drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n", in intel_dsb_dump()
207 crtc->base.base.id, crtc->base.name, dsb->id); in intel_dsb_dump()
208 for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) in intel_dsb_dump()
211 intel_dsb_buffer_read(&dsb->dsb_buf, i), in intel_dsb_dump()
212 intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), in intel_dsb_dump()
213 intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), in intel_dsb_dump()
214 intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); in intel_dsb_dump()
224 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) in intel_dsb_emit() argument
226 if (!assert_dsb_has_room(dsb)) in intel_dsb_emit()
230 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_emit()
232 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_emit()
233 dsb->ins[0] = ldw; in intel_dsb_emit()
234 dsb->ins[1] = udw; in intel_dsb_emit()
236 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]); in intel_dsb_emit()
237 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]); in intel_dsb_emit()
240 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, in intel_dsb_prev_ins_is_write() argument
250 if (dsb->free_pos == 0) in intel_dsb_prev_ins_is_write()
253 prev_opcode = dsb->ins[1] & ~DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
254 prev_reg = dsb->ins[1] & DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
259 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_indexed_write() argument
261 return intel_dsb_prev_ins_is_write(dsb, in intel_dsb_prev_ins_is_indexed_write()
267 * intel_dsb_reg_write_indexed() - Emit indexed register write to the DSB context
268 * @dsb: DSB context
273 * buffer of DSB.
279 void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, in intel_dsb_reg_write_indexed() argument
293 * As every instruction is 8 byte aligned the index of dsb instruction in intel_dsb_reg_write_indexed()
298 if (!intel_dsb_prev_ins_is_indexed_write(dsb, reg)) in intel_dsb_reg_write_indexed()
299 intel_dsb_emit(dsb, 0, /* count */ in intel_dsb_reg_write_indexed()
303 if (!assert_dsb_has_room(dsb)) in intel_dsb_reg_write_indexed()
307 dsb->ins[0]++; in intel_dsb_reg_write_indexed()
308 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, in intel_dsb_reg_write_indexed()
309 dsb->ins[0]); in intel_dsb_reg_write_indexed()
311 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); in intel_dsb_reg_write_indexed()
313 if (dsb->free_pos & 0x1) in intel_dsb_reg_write_indexed()
314 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); in intel_dsb_reg_write_indexed()
317 void intel_dsb_reg_write(struct intel_dsb *dsb, in intel_dsb_reg_write() argument
320 intel_dsb_emit(dsb, val, in intel_dsb_reg_write()
335 void intel_dsb_reg_write_masked(struct intel_dsb *dsb, in intel_dsb_reg_write_masked() argument
338 intel_dsb_emit(dsb, val, in intel_dsb_reg_write_masked()
344 void intel_dsb_noop(struct intel_dsb *dsb, int count) in intel_dsb_noop() argument
349 intel_dsb_emit(dsb, 0, in intel_dsb_noop()
353 void intel_dsb_nonpost_start(struct intel_dsb *dsb) in intel_dsb_nonpost_start() argument
355 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_start()
358 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_start()
360 intel_dsb_noop(dsb, 4); in intel_dsb_nonpost_start()
363 void intel_dsb_nonpost_end(struct intel_dsb *dsb) in intel_dsb_nonpost_end() argument
365 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_end()
368 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_end()
370 intel_dsb_noop(dsb, 4); in intel_dsb_nonpost_end()
373 void intel_dsb_interrupt(struct intel_dsb *dsb) in intel_dsb_interrupt() argument
375 intel_dsb_emit(dsb, 0, in intel_dsb_interrupt()
379 void intel_dsb_wait_usec(struct intel_dsb *dsb, int count) in intel_dsb_wait_usec() argument
381 intel_dsb_emit(dsb, count, in intel_dsb_wait_usec()
385 void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count) in intel_dsb_wait_vblanks() argument
387 intel_dsb_emit(dsb, count, in intel_dsb_wait_vblanks()
391 static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb, in intel_dsb_emit_wait_dsl() argument
397 intel_dsb_emit(dsb, lower_32_bits(window), in intel_dsb_emit_wait_dsl()
403 struct intel_dsb *dsb, in intel_dsb_wait_dsl() argument
407 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait_dsl()
416 intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_IN, in intel_dsb_wait_dsl()
419 intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, in intel_dsb_wait_dsl()
426 struct intel_dsb *dsb, in assert_dsl_ok() argument
429 struct intel_crtc *crtc = dsb->crtc; in assert_dsl_ok()
437 "[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d (vt=%d)\n", in assert_dsl_ok()
438 crtc->base.base.id, crtc->base.name, dsb->id, in assert_dsl_ok()
443 struct intel_dsb *dsb, in intel_dsb_wait_scanline_in() argument
446 assert_dsl_ok(state, dsb, start, end); in intel_dsb_wait_scanline_in()
448 intel_dsb_wait_dsl(state, dsb, in intel_dsb_wait_scanline_in()
454 struct intel_dsb *dsb, in intel_dsb_wait_scanline_out() argument
457 assert_dsl_ok(state, dsb, start, end); in intel_dsb_wait_scanline_out()
459 intel_dsb_wait_dsl(state, dsb, in intel_dsb_wait_scanline_out()
464 static void intel_dsb_align_tail(struct intel_dsb *dsb) in intel_dsb_align_tail() argument
468 tail = dsb->free_pos * 4; in intel_dsb_align_tail()
472 intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, in intel_dsb_align_tail()
475 dsb->free_pos = aligned_tail / 4; in intel_dsb_align_tail()
478 void intel_dsb_finish(struct intel_dsb *dsb) in intel_dsb_finish() argument
480 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_finish()
483 * DSB_FORCE_DEWAKE remains active even after DSB is in intel_dsb_finish()
488 intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0); in intel_dsb_finish()
489 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), in intel_dsb_finish()
492 intel_dsb_align_tail(dsb); in intel_dsb_finish()
494 intel_dsb_buffer_flush_map(&dsb->dsb_buf); in intel_dsb_finish()
532 struct intel_dsb *dsb) in intel_dsb_vblank_evade() argument
534 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_vblank_evade()
544 intel_dsb_wait_scanline_out(state, dsb, start, end); in intel_dsb_vblank_evade()
548 intel_dsb_wait_scanline_out(state, dsb, start, end); in intel_dsb_vblank_evade()
552 intel_dsb_wait_scanline_out(state, dsb, start, end); in intel_dsb_vblank_evade()
557 struct intel_dsb *dsb, in _intel_dsb_chain() argument
562 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_chain()
566 if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) in _intel_dsb_chain()
573 intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), in _intel_dsb_chain()
576 intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id), in _intel_dsb_chain()
579 intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id), in _intel_dsb_chain()
587 intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), in _intel_dsb_chain()
592 intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), in _intel_dsb_chain()
595 intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), in _intel_dsb_chain()
600 * Keep DEwake alive via the first DSB, in in _intel_dsb_chain()
603 * DSB won't do its job. in _intel_dsb_chain()
605 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_chain()
608 intel_dsb_wait_scanline_out(state, dsb, in _intel_dsb_chain()
615 struct intel_dsb *dsb, in intel_dsb_chain() argument
619 _intel_dsb_chain(state, dsb, chained_dsb, in intel_dsb_chain()
624 struct intel_dsb *dsb) in intel_dsb_wait_vblank_delay() argument
626 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait_vblank_delay()
631 intel_dsb_wait_usec(dsb, usecs); in intel_dsb_wait_vblank_delay()
634 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, in _intel_dsb_commit() argument
637 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_commit()
642 tail = dsb->free_pos * 4; in _intel_dsb_commit()
646 if (is_dsb_busy(display, pipe, dsb->id)) { in _intel_dsb_commit()
647 drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", in _intel_dsb_commit()
648 crtc->base.base.id, crtc->base.name, dsb->id); in _intel_dsb_commit()
652 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), in _intel_dsb_commit()
655 intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), in _intel_dsb_commit()
656 dsb->chicken); in _intel_dsb_commit()
658 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), in _intel_dsb_commit()
662 intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), in _intel_dsb_commit()
663 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); in _intel_dsb_commit()
668 intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), in _intel_dsb_commit()
679 intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_commit()
684 intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), in _intel_dsb_commit()
685 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); in _intel_dsb_commit()
689 * intel_dsb_commit() - Trigger workload execution of DSB.
690 * @dsb: DSB context
693 * This function is used to do actual write to hardware using DSB.
695 void intel_dsb_commit(struct intel_dsb *dsb, in intel_dsb_commit() argument
698 _intel_dsb_commit(dsb, in intel_dsb_commit()
700 wait_for_vblank ? dsb->hw_dewake_scanline : -1); in intel_dsb_commit()
703 void intel_dsb_wait(struct intel_dsb *dsb) in intel_dsb_wait() argument
705 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait()
709 if (wait_for(!is_dsb_busy(display, pipe, dsb->id), 1)) { in intel_dsb_wait()
710 u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); in intel_dsb_wait()
712 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), in intel_dsb_wait()
716 "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n", in intel_dsb_wait()
717 crtc->base.base.id, crtc->base.name, dsb->id, in intel_dsb_wait()
718 intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
719 intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
720 intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset); in intel_dsb_wait()
722 intel_dsb_dump(dsb); in intel_dsb_wait()
726 dsb->free_pos = 0; in intel_dsb_wait()
727 dsb->ins_start_offset = 0; in intel_dsb_wait()
728 dsb->ins[0] = 0; in intel_dsb_wait()
729 dsb->ins[1] = 0; in intel_dsb_wait()
731 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); in intel_dsb_wait()
733 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), in intel_dsb_wait()
738 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
741 * @dsb_id: the DSB engine to use
744 * This function prepare the command buffer which is used to store dsb
748 * DSB context, NULL on failure
757 struct intel_dsb *dsb; in intel_dsb_prepare() local
766 dsb = kzalloc(sizeof(*dsb), GFP_KERNEL); in intel_dsb_prepare()
767 if (!dsb) in intel_dsb_prepare()
775 if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size)) in intel_dsb_prepare()
780 dsb->id = dsb_id; in intel_dsb_prepare()
781 dsb->crtc = crtc; in intel_dsb_prepare()
782 dsb->size = size / 4; /* in dwords */ in intel_dsb_prepare()
784 dsb->chicken = dsb_chicken(state, crtc); in intel_dsb_prepare()
785 dsb->hw_dewake_scanline = in intel_dsb_prepare()
788 return dsb; in intel_dsb_prepare()
792 kfree(dsb); in intel_dsb_prepare()
795 … "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", in intel_dsb_prepare()
802 * intel_dsb_cleanup() - To cleanup DSB context.
803 * @dsb: DSB context
805 * This function cleanup the DSB context by unpinning and releasing
808 void intel_dsb_cleanup(struct intel_dsb *dsb) in intel_dsb_cleanup() argument
810 intel_dsb_buffer_cleanup(&dsb->dsb_buf); in intel_dsb_cleanup()
811 kfree(dsb); in intel_dsb_cleanup()
842 drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", in intel_dsb_irq_handler()