Lines Matching full:i915
68 void (*enable)(struct drm_i915_private *i915,
77 void (*disable)(struct drm_i915_private *i915,
85 bool (*get_hw_state)(struct drm_i915_private *i915,
93 int (*get_freq)(struct drm_i915_private *i915,
112 void (*update_ref_clks)(struct drm_i915_private *i915);
120 intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, in intel_atomic_duplicate_dpll_state() argument
127 for_each_shared_dpll(i915, pll, i) in intel_atomic_duplicate_dpll_state()
150 * @i915: i915 device instance
157 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, in intel_get_shared_dpll_by_id() argument
163 for_each_shared_dpll(i915, pll, i) { in intel_get_shared_dpll_by_id()
173 void assert_shared_dpll(struct drm_i915_private *i915, in assert_shared_dpll() argument
177 struct intel_display *display = &i915->display; in assert_shared_dpll()
185 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); in assert_shared_dpll()
203 intel_combo_pll_enable_reg(struct drm_i915_private *i915, in intel_combo_pll_enable_reg() argument
206 if (IS_DG1(i915)) in intel_combo_pll_enable_reg()
208 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in intel_combo_pll_enable_reg()
216 intel_tc_pll_enable_reg(struct drm_i915_private *i915, in intel_tc_pll_enable_reg() argument
222 if (IS_ALDERLAKE_P(i915)) in intel_tc_pll_enable_reg()
228 static void _intel_enable_shared_dpll(struct drm_i915_private *i915, in _intel_enable_shared_dpll() argument
232 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in _intel_enable_shared_dpll()
234 pll->info->funcs->enable(i915, pll, &pll->state.hw_state); in _intel_enable_shared_dpll()
238 static void _intel_disable_shared_dpll(struct drm_i915_private *i915, in _intel_disable_shared_dpll() argument
241 pll->info->funcs->disable(i915, pll); in _intel_disable_shared_dpll()
245 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); in _intel_disable_shared_dpll()
257 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_enable_shared_dpll() local
262 if (drm_WARN_ON(&i915->drm, pll == NULL)) in intel_enable_shared_dpll()
265 mutex_lock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
268 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
269 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
274 drm_dbg_kms(&i915->drm, in intel_enable_shared_dpll()
280 drm_WARN_ON(&i915->drm, !pll->on); in intel_enable_shared_dpll()
281 assert_shared_dpll_enabled(i915, pll); in intel_enable_shared_dpll()
284 drm_WARN_ON(&i915->drm, pll->on); in intel_enable_shared_dpll()
286 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); in intel_enable_shared_dpll()
288 _intel_enable_shared_dpll(i915, pll); in intel_enable_shared_dpll()
291 mutex_unlock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
303 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_disable_shared_dpll() local
308 if (DISPLAY_VER(i915) < 5) in intel_disable_shared_dpll()
314 mutex_lock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
315 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
320 drm_dbg_kms(&i915->drm, in intel_disable_shared_dpll()
325 assert_shared_dpll_enabled(i915, pll); in intel_disable_shared_dpll()
326 drm_WARN_ON(&i915->drm, !pll->on); in intel_disable_shared_dpll()
332 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); in intel_disable_shared_dpll()
334 _intel_disable_shared_dpll(i915, pll); in intel_disable_shared_dpll()
337 mutex_unlock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
341 intel_dpll_mask_all(struct drm_i915_private *i915) in intel_dpll_mask_all() argument
347 for_each_shared_dpll(i915, pll, i) { in intel_dpll_mask_all()
348 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); in intel_dpll_mask_all()
362 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_find_shared_dpll() local
363 unsigned long dpll_mask_all = intel_dpll_mask_all(i915); in intel_find_shared_dpll()
370 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); in intel_find_shared_dpll()
375 pll = intel_get_shared_dpll_by_id(i915, id); in intel_find_shared_dpll()
389 drm_dbg_kms(&i915->drm, in intel_find_shared_dpll()
401 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", in intel_find_shared_dpll()
423 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_reference_shared_dpll_crtc() local
425 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); in intel_reference_shared_dpll_crtc()
429 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n", in intel_reference_shared_dpll_crtc()
462 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_unreference_shared_dpll_crtc() local
464 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); in intel_unreference_shared_dpll_crtc()
468 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n", in intel_unreference_shared_dpll_crtc()
512 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_swap_state() local
520 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_swap_state()
524 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, in ibx_pch_dpll_get_hw_state() argument
533 wakeref = intel_display_power_get_if_enabled(i915, in ibx_pch_dpll_get_hw_state()
538 val = intel_de_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
540 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
541 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
543 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in ibx_pch_dpll_get_hw_state()
548 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) in ibx_assert_pch_refclk_enabled() argument
550 struct intel_display *display = &i915->display; in ibx_assert_pch_refclk_enabled()
561 static void ibx_pch_dpll_enable(struct drm_i915_private *i915, in ibx_pch_dpll_enable() argument
569 ibx_assert_pch_refclk_enabled(i915); in ibx_pch_dpll_enable()
571 intel_de_write(i915, PCH_FP0(id), hw_state->fp0); in ibx_pch_dpll_enable()
572 intel_de_write(i915, PCH_FP1(id), hw_state->fp1); in ibx_pch_dpll_enable()
574 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
577 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
585 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
586 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
590 static void ibx_pch_dpll_disable(struct drm_i915_private *i915, in ibx_pch_dpll_disable() argument
595 intel_de_write(i915, PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
596 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_disable()
613 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ibx_get_dpll() local
617 if (HAS_PCH_IBX(i915)) { in ibx_get_dpll()
620 pll = intel_get_shared_dpll_by_id(i915, id); in ibx_get_dpll()
622 drm_dbg_kms(&i915->drm, in ibx_get_dpll()
691 static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, in hsw_ddi_wrpll_enable() argument
698 intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll); in hsw_ddi_wrpll_enable()
699 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
703 static void hsw_ddi_spll_enable(struct drm_i915_private *i915, in hsw_ddi_spll_enable() argument
709 intel_de_write(i915, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
710 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_enable()
714 static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, in hsw_ddi_wrpll_disable() argument
719 intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); in hsw_ddi_wrpll_disable()
720 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
726 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
727 intel_init_pch_refclk(i915); in hsw_ddi_wrpll_disable()
730 static void hsw_ddi_spll_disable(struct drm_i915_private *i915, in hsw_ddi_spll_disable() argument
735 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); in hsw_ddi_spll_disable()
736 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_disable()
742 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
743 intel_init_pch_refclk(i915); in hsw_ddi_spll_disable()
746 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_wrpll_get_hw_state() argument
755 wakeref = intel_display_power_get_if_enabled(i915, in hsw_ddi_wrpll_get_hw_state()
760 val = intel_de_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
763 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in hsw_ddi_wrpll_get_hw_state()
768 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_spll_get_hw_state() argument
776 wakeref = intel_display_power_get_if_enabled(i915, in hsw_ddi_spll_get_hw_state()
781 val = intel_de_read(i915, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
784 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in hsw_ddi_spll_get_hw_state()
995 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, in hsw_ddi_wrpll_get_freq() argument
1007 if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) { in hsw_ddi_wrpll_get_freq()
1008 refclk = i915->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
1018 refclk = i915->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1040 struct drm_i915_private *i915 = to_i915(state->base.dev); in hsw_ddi_wrpll_compute_dpll() local
1053 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1075 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_compute_dpll() local
1084 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", in hsw_ddi_lcpll_compute_dpll()
1093 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_get_dpll() local
1113 pll = intel_get_shared_dpll_by_id(i915, pll_id); in hsw_ddi_lcpll_get_dpll()
1121 static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, in hsw_ddi_lcpll_get_freq() argument
1138 drm_WARN(&i915->drm, 1, "bad port clock sel\n"); in hsw_ddi_lcpll_get_freq()
1173 static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, in hsw_ddi_spll_get_freq() argument
1191 drm_WARN(&i915->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1241 static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) in hsw_update_dpll_ref_clks() argument
1243 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1245 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1246 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1248 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1284 static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, in hsw_ddi_lcpll_enable() argument
1290 static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, in hsw_ddi_lcpll_disable() argument
1295 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_lcpll_get_hw_state() argument
1363 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, in skl_ddi_pll_write_ctrl1() argument
1369 intel_de_rmw(i915, DPLL_CTRL1, in skl_ddi_pll_write_ctrl1()
1374 intel_de_posting_read(i915, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1377 static void skl_ddi_pll_enable(struct drm_i915_private *i915, in skl_ddi_pll_enable() argument
1385 skl_ddi_pll_write_ctrl1(i915, pll, hw_state); in skl_ddi_pll_enable()
1387 intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1); in skl_ddi_pll_enable()
1388 intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2); in skl_ddi_pll_enable()
1389 intel_de_posting_read(i915, regs[id].cfgcr1); in skl_ddi_pll_enable()
1390 intel_de_posting_read(i915, regs[id].cfgcr2); in skl_ddi_pll_enable()
1393 intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
1395 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) in skl_ddi_pll_enable()
1396 drm_err(&i915->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1399 static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, in skl_ddi_dpll0_enable() argument
1405 skl_ddi_pll_write_ctrl1(i915, pll, hw_state); in skl_ddi_dpll0_enable()
1408 static void skl_ddi_pll_disable(struct drm_i915_private *i915, in skl_ddi_pll_disable() argument
1415 intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); in skl_ddi_pll_disable()
1416 intel_de_posting_read(i915, regs[id].ctl); in skl_ddi_pll_disable()
1419 static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, in skl_ddi_dpll0_disable() argument
1424 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, in skl_ddi_pll_get_hw_state() argument
1435 wakeref = intel_display_power_get_if_enabled(i915, in skl_ddi_pll_get_hw_state()
1442 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1446 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1451 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1452 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1457 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in skl_ddi_pll_get_hw_state()
1462 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, in skl_ddi_dpll0_get_hw_state() argument
1473 wakeref = intel_display_power_get_if_enabled(i915, in skl_ddi_dpll0_get_hw_state()
1481 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_dpll0_get_hw_state()
1482 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) in skl_ddi_dpll0_get_hw_state()
1485 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
1491 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in skl_ddi_dpll0_get_hw_state()
1735 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, in skl_ddi_wrpll_get_freq() argument
1740 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1767 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); in skl_ddi_wrpll_get_freq()
1801 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in skl_ddi_wrpll_get_freq()
1809 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_ddi_hdmi_pll_dividers() local
1815 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1839 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1883 static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, in skl_ddi_lcpll_get_freq() argument
1911 drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); in skl_ddi_lcpll_get_freq()
1962 static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, in skl_ddi_pll_get_freq() argument
1973 return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state); in skl_ddi_pll_get_freq()
1975 return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state); in skl_ddi_pll_get_freq()
1978 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) in skl_update_dpll_ref_clks() argument
1981 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
2037 static void bxt_ddi_pll_enable(struct drm_i915_private *i915, in bxt_ddi_pll_enable() argument
2041 struct intel_display *display = &i915->display; in bxt_ddi_pll_enable()
2051 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); in bxt_ddi_pll_enable()
2053 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_enable()
2054 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_enable()
2057 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_enable()
2059 drm_err(&i915->drm, in bxt_ddi_pll_enable()
2064 intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), in bxt_ddi_pll_enable()
2068 intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), in bxt_ddi_pll_enable()
2072 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0), in bxt_ddi_pll_enable()
2076 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1), in bxt_ddi_pll_enable()
2080 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2), in bxt_ddi_pll_enable()
2084 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3), in bxt_ddi_pll_enable()
2088 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_enable()
2093 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp); in bxt_ddi_pll_enable()
2096 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8), in bxt_ddi_pll_enable()
2099 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9), in bxt_ddi_pll_enable()
2102 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_enable()
2106 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp); in bxt_ddi_pll_enable()
2109 temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_enable()
2111 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
2114 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
2117 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); in bxt_ddi_pll_enable()
2118 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2120 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), in bxt_ddi_pll_enable()
2122 drm_err(&i915->drm, "PLL %d not locked\n", port); in bxt_ddi_pll_enable()
2124 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_enable()
2125 temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0)); in bxt_ddi_pll_enable()
2127 intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp); in bxt_ddi_pll_enable()
2134 temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); in bxt_ddi_pll_enable()
2138 intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); in bxt_ddi_pll_enable()
2141 static void bxt_ddi_pll_disable(struct drm_i915_private *i915, in bxt_ddi_pll_disable() argument
2146 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); in bxt_ddi_pll_disable()
2147 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_disable()
2149 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_disable()
2150 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_disable()
2153 if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_disable()
2155 drm_err(&i915->drm, in bxt_ddi_pll_disable()
2160 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, in bxt_ddi_pll_get_hw_state() argument
2164 struct intel_display *display = &i915->display; in bxt_ddi_pll_get_hw_state()
2175 wakeref = intel_display_power_get_if_enabled(i915, in bxt_ddi_pll_get_hw_state()
2182 val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_get_hw_state()
2186 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2189 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2192 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2195 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2198 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2201 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2204 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2209 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2212 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2215 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2224 hw_state->pcsdw12 = intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2226 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2227 drm_dbg(&i915->drm, in bxt_ddi_pll_get_hw_state()
2230 intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2237 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in bxt_ddi_pll_get_hw_state()
2258 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_pll_dividers() local
2268 drm_WARN_ON(&i915->drm, clk_div->m1 != 2); in bxt_ddi_hdmi_pll_dividers()
2276 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_dp_pll_dividers() local
2287 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2289 drm_WARN_ON(&i915->drm, clk_div->vco == 0 || in bxt_ddi_dp_pll_dividers()
2296 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_set_dpll_hw_state() local
2320 drm_err(&i915->drm, "Invalid VCO\n"); in bxt_ddi_set_dpll_hw_state()
2361 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, in bxt_ddi_pll_get_freq() argument
2377 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2393 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_set_dpll_hw_state() local
2403 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2430 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in bxt_get_dpll() local
2436 pll = intel_get_shared_dpll_by_id(i915, id); in bxt_get_dpll()
2438 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", in bxt_get_dpll()
2449 static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) in bxt_update_dpll_ref_clks() argument
2451 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2452 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2604 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) in ehl_combo_pll_div_frac_wa_needed() argument
2606 return ((IS_ELKHARTLAKE(i915) && in ehl_combo_pll_div_frac_wa_needed()
2607 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || in ehl_combo_pll_div_frac_wa_needed()
2608 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && in ehl_combo_pll_div_frac_wa_needed()
2609 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2701 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_dp_combo_pll() local
2703 i915->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2723 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_tbt_pll() local
2725 if (DISPLAY_VER(i915) >= 12) { in icl_calc_tbt_pll()
2726 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2728 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2739 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2741 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2756 static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_tbt_pll_get_freq() argument
2764 drm_WARN_ON(&i915->drm, 1); in icl_ddi_tbt_pll_get_freq()
2769 static int icl_wrpll_ref_clock(struct drm_i915_private *i915) in icl_wrpll_ref_clock() argument
2771 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2787 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_wrpll() local
2788 int ref_clock = icl_wrpll_ref_clock(i915); in icl_calc_wrpll()
2827 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_combo_pll_get_freq() argument
2832 int ref_clock = icl_wrpll_ref_clock(i915); in icl_ddi_combo_pll_get_freq()
2878 if (ehl_combo_pll_div_frac_wa_needed(i915)) in icl_ddi_combo_pll_get_freq()
2883 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in icl_ddi_combo_pll_get_freq()
2889 static void icl_calc_dpll_state(struct drm_i915_private *i915, in icl_calc_dpll_state() argument
2896 if (ehl_combo_pll_div_frac_wa_needed(i915)) in icl_calc_dpll_state()
2907 if (DISPLAY_VER(i915) >= 12) in icl_calc_dpll_state()
2912 if (i915->display.vbt.override_afc_startup) in icl_calc_dpll_state()
2913 hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); in icl_calc_dpll_state()
2999 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_mg_pll_state() local
3001 int refclk_khz = i915->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3011 bool is_dkl = DISPLAY_VER(i915) >= 12; in icl_calc_mg_pll_state()
3109 if (i915->display.vbt.override_afc_startup) { in icl_calc_mg_pll_state()
3110 u8 val = i915->display.vbt.override_afc_startup_val; in icl_calc_mg_pll_state()
3200 static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_mg_pll_get_freq() argument
3208 ref_clock = i915->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3210 if (DISPLAY_VER(i915) >= 12) { in icl_ddi_mg_pll_get_freq()
3315 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_compute_combo_phy_dpll() local
3332 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3337 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, in icl_compute_combo_phy_dpll()
3348 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_get_combo_phy_dpll() local
3356 if (IS_ALDERLAKE_S(i915)) { in icl_get_combo_phy_dpll()
3362 } else if (IS_DG1(i915)) { in icl_get_combo_phy_dpll()
3372 } else if (IS_ROCKETLAKE(i915)) { in icl_get_combo_phy_dpll()
3377 } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_get_combo_phy_dpll()
3407 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_tc_phy_dplls() local
3422 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3436 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, in icl_compute_tc_phy_dplls()
3540 static bool mg_pll_get_hw_state(struct drm_i915_private *i915, in mg_pll_get_hw_state() argument
3551 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_get_hw_state()
3553 wakeref = intel_display_power_get_if_enabled(i915, in mg_pll_get_hw_state()
3558 val = intel_de_read(i915, enable_reg); in mg_pll_get_hw_state()
3562 hw_state->mg_refclkin_ctl = intel_de_read(i915, in mg_pll_get_hw_state()
3567 intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state()
3572 intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state()
3579 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3580 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3581 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3582 hw_state->mg_pll_frac_lock = intel_de_read(i915, in mg_pll_get_hw_state()
3584 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3586 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3588 intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); in mg_pll_get_hw_state()
3590 if (i915->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3603 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in mg_pll_get_hw_state()
3607 static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, in dkl_pll_get_hw_state() argument
3618 wakeref = intel_display_power_get_if_enabled(i915, in dkl_pll_get_hw_state()
3623 val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); in dkl_pll_get_hw_state()
3631 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, in dkl_pll_get_hw_state()
3636 intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); in dkl_pll_get_hw_state()
3644 intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); in dkl_pll_get_hw_state()
3648 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3650 if (i915->display.vbt.override_afc_startup) in dkl_pll_get_hw_state()
3654 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3658 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3664 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3669 intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_get_hw_state()
3675 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in dkl_pll_get_hw_state()
3679 static bool icl_pll_get_hw_state(struct drm_i915_private *i915, in icl_pll_get_hw_state() argument
3690 wakeref = intel_display_power_get_if_enabled(i915, in icl_pll_get_hw_state()
3695 val = intel_de_read(i915, enable_reg); in icl_pll_get_hw_state()
3699 if (IS_ALDERLAKE_S(i915)) { in icl_pll_get_hw_state()
3700 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3701 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3702 } else if (IS_DG1(i915)) { in icl_pll_get_hw_state()
3703 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3704 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3705 } else if (IS_ROCKETLAKE(i915)) { in icl_pll_get_hw_state()
3706 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3708 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3710 } else if (DISPLAY_VER(i915) >= 12) { in icl_pll_get_hw_state()
3711 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3713 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3715 if (i915->display.vbt.override_afc_startup) { in icl_pll_get_hw_state()
3716 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3720 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_pll_get_hw_state()
3722 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3724 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3727 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3729 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3736 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in icl_pll_get_hw_state()
3740 static bool combo_pll_get_hw_state(struct drm_i915_private *i915, in combo_pll_get_hw_state() argument
3744 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_get_hw_state()
3746 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg); in combo_pll_get_hw_state()
3749 static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, in tbt_pll_get_hw_state() argument
3753 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE); in tbt_pll_get_hw_state()
3756 static void icl_dpll_write(struct drm_i915_private *i915, in icl_dpll_write() argument
3763 if (IS_ALDERLAKE_S(i915)) { in icl_dpll_write()
3766 } else if (IS_DG1(i915)) { in icl_dpll_write()
3769 } else if (IS_ROCKETLAKE(i915)) { in icl_dpll_write()
3772 } else if (DISPLAY_VER(i915) >= 12) { in icl_dpll_write()
3777 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_dpll_write()
3787 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3788 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3789 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && in icl_dpll_write()
3791 if (i915->display.vbt.override_afc_startup && in icl_dpll_write()
3793 intel_de_rmw(i915, div0_reg, in icl_dpll_write()
3795 intel_de_posting_read(i915, cfgcr1_reg); in icl_dpll_write()
3798 static void icl_mg_pll_write(struct drm_i915_private *i915, in icl_mg_pll_write() argument
3810 intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port), in icl_mg_pll_write()
3813 intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port), in icl_mg_pll_write()
3817 intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port), in icl_mg_pll_write()
3824 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3825 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3826 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3827 intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port), in icl_mg_pll_write()
3829 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3831 intel_de_rmw(i915, MG_PLL_BIAS(tc_port), in icl_mg_pll_write()
3834 intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port), in icl_mg_pll_write()
3838 intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); in icl_mg_pll_write()
3841 static void dkl_pll_write(struct drm_i915_private *i915, in dkl_pll_write() argument
3853 val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); in dkl_pll_write()
3856 intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val); in dkl_pll_write()
3858 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); in dkl_pll_write()
3861 intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); in dkl_pll_write()
3863 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); in dkl_pll_write()
3869 intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val); in dkl_pll_write()
3872 if (i915->display.vbt.override_afc_startup) in dkl_pll_write()
3874 intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, in dkl_pll_write()
3877 val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_write()
3881 intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val); in dkl_pll_write()
3883 val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_write()
3889 intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val); in dkl_pll_write()
3891 val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_write()
3895 intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val); in dkl_pll_write()
3897 val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_write()
3901 intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); in dkl_pll_write()
3903 intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_write()
3906 static void icl_pll_power_enable(struct drm_i915_private *i915, in icl_pll_power_enable() argument
3910 intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE); in icl_pll_power_enable()
3916 if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_power_enable()
3917 drm_err(&i915->drm, "PLL %d Power not enabled\n", in icl_pll_power_enable()
3921 static void icl_pll_enable(struct drm_i915_private *i915, in icl_pll_enable() argument
3925 intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE); in icl_pll_enable()
3928 if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1)) in icl_pll_enable()
3929 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); in icl_pll_enable()
3932 static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) in adlp_cmtg_clock_gating_wa() argument
3936 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) || in adlp_cmtg_clock_gating_wa()
3950 val = intel_de_read(i915, TRANS_CMTG_CHICKEN); in adlp_cmtg_clock_gating_wa()
3951 val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING); in adlp_cmtg_clock_gating_wa()
3952 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING)) in adlp_cmtg_clock_gating_wa()
3953 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); in adlp_cmtg_clock_gating_wa()
3956 static void combo_pll_enable(struct drm_i915_private *i915, in combo_pll_enable() argument
3961 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_enable()
3963 icl_pll_power_enable(i915, pll, enable_reg); in combo_pll_enable()
3965 icl_dpll_write(i915, pll, hw_state); in combo_pll_enable()
3973 icl_pll_enable(i915, pll, enable_reg); in combo_pll_enable()
3975 adlp_cmtg_clock_gating_wa(i915, pll); in combo_pll_enable()
3980 static void tbt_pll_enable(struct drm_i915_private *i915, in tbt_pll_enable() argument
3986 icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3988 icl_dpll_write(i915, pll, hw_state); in tbt_pll_enable()
3996 icl_pll_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
4001 static void mg_pll_enable(struct drm_i915_private *i915, in mg_pll_enable() argument
4006 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_enable()
4008 icl_pll_power_enable(i915, pll, enable_reg); in mg_pll_enable()
4010 if (DISPLAY_VER(i915) >= 12) in mg_pll_enable()
4011 dkl_pll_write(i915, pll, hw_state); in mg_pll_enable()
4013 icl_mg_pll_write(i915, pll, hw_state); in mg_pll_enable()
4021 icl_pll_enable(i915, pll, enable_reg); in mg_pll_enable()
4026 static void icl_pll_disable(struct drm_i915_private *i915, in icl_pll_disable() argument
4038 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); in icl_pll_disable()
4041 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1)) in icl_pll_disable()
4042 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); in icl_pll_disable()
4046 intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0); in icl_pll_disable()
4052 if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_disable()
4053 drm_err(&i915->drm, "PLL %d Power not disabled\n", in icl_pll_disable()
4057 static void combo_pll_disable(struct drm_i915_private *i915, in combo_pll_disable() argument
4060 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_disable()
4062 icl_pll_disable(i915, pll, enable_reg); in combo_pll_disable()
4065 static void tbt_pll_disable(struct drm_i915_private *i915, in tbt_pll_disable() argument
4068 icl_pll_disable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_disable()
4071 static void mg_pll_disable(struct drm_i915_private *i915, in mg_pll_disable() argument
4074 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_disable()
4076 icl_pll_disable(i915, pll, enable_reg); in mg_pll_disable()
4079 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) in icl_update_dpll_ref_clks() argument
4082 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
4303 * @i915: i915 device
4305 * Initialize shared DPLLs for @i915.
4307 void intel_shared_dpll_init(struct drm_i915_private *i915) in intel_shared_dpll_init() argument
4313 mutex_init(&i915->display.dpll.lock); in intel_shared_dpll_init()
4315 if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915)) in intel_shared_dpll_init()
4318 else if (IS_ALDERLAKE_P(i915)) in intel_shared_dpll_init()
4320 else if (IS_ALDERLAKE_S(i915)) in intel_shared_dpll_init()
4322 else if (IS_DG1(i915)) in intel_shared_dpll_init()
4324 else if (IS_ROCKETLAKE(i915)) in intel_shared_dpll_init()
4326 else if (DISPLAY_VER(i915) >= 12) in intel_shared_dpll_init()
4328 else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) in intel_shared_dpll_init()
4330 else if (DISPLAY_VER(i915) >= 11) in intel_shared_dpll_init()
4332 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) in intel_shared_dpll_init()
4334 else if (DISPLAY_VER(i915) == 9) in intel_shared_dpll_init()
4336 else if (HAS_DDI(i915)) in intel_shared_dpll_init()
4338 else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) in intel_shared_dpll_init()
4347 if (drm_WARN_ON(&i915->drm, in intel_shared_dpll_init()
4348 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4352 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) in intel_shared_dpll_init()
4355 i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4356 i915->display.dpll.shared_dplls[i].index = i; in intel_shared_dpll_init()
4359 i915->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4360 i915->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4381 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_compute_shared_dplls() local
4382 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_compute_shared_dplls()
4384 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_compute_shared_dplls()
4414 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_reserve_shared_dplls() local
4415 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_reserve_shared_dplls()
4417 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_reserve_shared_dplls()
4437 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_release_shared_dplls() local
4438 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_release_shared_dplls()
4466 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_update_active_dpll() local
4467 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_update_active_dpll()
4469 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_update_active_dpll()
4477 * @i915: i915 device
4483 int intel_dpll_get_freq(struct drm_i915_private *i915, in intel_dpll_get_freq() argument
4487 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) in intel_dpll_get_freq()
4490 return pll->info->funcs->get_freq(i915, pll, dpll_hw_state); in intel_dpll_get_freq()
4495 * @i915: i915 device
4501 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, in intel_dpll_get_hw_state() argument
4505 return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state); in intel_dpll_get_hw_state()
4508 static void readout_dpll_hw_state(struct drm_i915_private *i915, in readout_dpll_hw_state() argument
4513 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4516 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in readout_dpll_hw_state()
4519 for_each_intel_crtc(&i915->drm, crtc) { in readout_dpll_hw_state()
4528 drm_dbg_kms(&i915->drm, in readout_dpll_hw_state()
4533 void intel_dpll_update_ref_clks(struct drm_i915_private *i915) in intel_dpll_update_ref_clks() argument
4535 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4536 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4539 void intel_dpll_readout_hw_state(struct drm_i915_private *i915) in intel_dpll_readout_hw_state() argument
4544 for_each_shared_dpll(i915, pll, i) in intel_dpll_readout_hw_state()
4545 readout_dpll_hw_state(i915, pll); in intel_dpll_readout_hw_state()
4548 static void sanitize_dpll_state(struct drm_i915_private *i915, in sanitize_dpll_state() argument
4554 adlp_cmtg_clock_gating_wa(i915, pll); in sanitize_dpll_state()
4559 drm_dbg_kms(&i915->drm, in sanitize_dpll_state()
4563 _intel_disable_shared_dpll(i915, pll); in sanitize_dpll_state()
4566 void intel_dpll_sanitize_state(struct drm_i915_private *i915) in intel_dpll_sanitize_state() argument
4571 for_each_shared_dpll(i915, pll, i) in intel_dpll_sanitize_state()
4572 sanitize_dpll_state(i915, pll); in intel_dpll_sanitize_state()
4577 * @i915: i915 drm device
4583 void intel_dpll_dump_hw_state(struct drm_i915_private *i915, in intel_dpll_dump_hw_state() argument
4587 if (i915->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4588 i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state); in intel_dpll_dump_hw_state()
4599 * @i915: i915 drm device
4607 bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, in intel_dpll_compare_hw_state() argument
4611 if (i915->display.dpll.mgr) { in intel_dpll_compare_hw_state()
4612 return i915->display.dpll.mgr->compare_hw_state(a, b); in intel_dpll_compare_hw_state()
4622 verify_single_dpll_state(struct drm_i915_private *i915, in verify_single_dpll_state() argument
4627 struct intel_display *display = &i915->display; in verify_single_dpll_state()
4632 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); in verify_single_dpll_state()
4688 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_state_verify() local
4695 verify_single_dpll_state(i915, new_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4718 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_verify_disabled() local
4722 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_verify_disabled()
4723 verify_single_dpll_state(i915, pll, NULL, NULL); in intel_shared_dpll_verify_disabled()