Lines Matching +full:min +full:- +full:state
1 // SPDX-License-Identifier: MIT
28 int (*crtc_compute_clock)(struct intel_atomic_state *state,
30 int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
36 int min, max; member
45 .dot = { .min = 25000, .max = 350000 },
46 .vco = { .min = 908000, .max = 1512000 },
47 .n = { .min = 2, .max = 16 },
48 .m = { .min = 96, .max = 140 },
49 .m1 = { .min = 18, .max = 26 },
50 .m2 = { .min = 6, .max = 16 },
51 .p = { .min = 4, .max = 128 },
52 .p1 = { .min = 2, .max = 33 },
58 .dot = { .min = 25000, .max = 350000 },
59 .vco = { .min = 908000, .max = 1512000 },
60 .n = { .min = 2, .max = 16 },
61 .m = { .min = 96, .max = 140 },
62 .m1 = { .min = 18, .max = 26 },
63 .m2 = { .min = 6, .max = 16 },
64 .p = { .min = 4, .max = 128 },
65 .p1 = { .min = 2, .max = 33 },
71 .dot = { .min = 25000, .max = 350000 },
72 .vco = { .min = 908000, .max = 1512000 },
73 .n = { .min = 2, .max = 16 },
74 .m = { .min = 96, .max = 140 },
75 .m1 = { .min = 18, .max = 26 },
76 .m2 = { .min = 6, .max = 16 },
77 .p = { .min = 4, .max = 128 },
78 .p1 = { .min = 1, .max = 6 },
84 .dot = { .min = 20000, .max = 400000 },
85 .vco = { .min = 1400000, .max = 2800000 },
86 .n = { .min = 1, .max = 6 },
87 .m = { .min = 70, .max = 120 },
88 .m1 = { .min = 8, .max = 18 },
89 .m2 = { .min = 3, .max = 7 },
90 .p = { .min = 5, .max = 80 },
91 .p1 = { .min = 1, .max = 8 },
97 .dot = { .min = 20000, .max = 400000 },
98 .vco = { .min = 1400000, .max = 2800000 },
99 .n = { .min = 1, .max = 6 },
100 .m = { .min = 70, .max = 120 },
101 .m1 = { .min = 8, .max = 18 },
102 .m2 = { .min = 3, .max = 7 },
103 .p = { .min = 7, .max = 98 },
104 .p1 = { .min = 1, .max = 8 },
111 .dot = { .min = 25000, .max = 270000 },
112 .vco = { .min = 1750000, .max = 3500000},
113 .n = { .min = 1, .max = 4 },
114 .m = { .min = 104, .max = 138 },
115 .m1 = { .min = 17, .max = 23 },
116 .m2 = { .min = 5, .max = 11 },
117 .p = { .min = 10, .max = 30 },
118 .p1 = { .min = 1, .max = 3},
126 .dot = { .min = 22000, .max = 400000 },
127 .vco = { .min = 1750000, .max = 3500000},
128 .n = { .min = 1, .max = 4 },
129 .m = { .min = 104, .max = 138 },
130 .m1 = { .min = 16, .max = 23 },
131 .m2 = { .min = 5, .max = 11 },
132 .p = { .min = 5, .max = 80 },
133 .p1 = { .min = 1, .max = 8},
139 .dot = { .min = 20000, .max = 115000 },
140 .vco = { .min = 1750000, .max = 3500000 },
141 .n = { .min = 1, .max = 3 },
142 .m = { .min = 104, .max = 138 },
143 .m1 = { .min = 17, .max = 23 },
144 .m2 = { .min = 5, .max = 11 },
145 .p = { .min = 28, .max = 112 },
146 .p1 = { .min = 2, .max = 8 },
153 .dot = { .min = 80000, .max = 224000 },
154 .vco = { .min = 1750000, .max = 3500000 },
155 .n = { .min = 1, .max = 3 },
156 .m = { .min = 104, .max = 138 },
157 .m1 = { .min = 17, .max = 23 },
158 .m2 = { .min = 5, .max = 11 },
159 .p = { .min = 14, .max = 42 },
160 .p1 = { .min = 2, .max = 6 },
167 .dot = { .min = 20000, .max = 400000},
168 .vco = { .min = 1700000, .max = 3500000 },
170 .n = { .min = 3, .max = 6 },
171 .m = { .min = 2, .max = 256 },
173 .m1 = { .min = 0, .max = 0 },
174 .m2 = { .min = 0, .max = 254 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
182 .dot = { .min = 20000, .max = 400000 },
183 .vco = { .min = 1700000, .max = 3500000 },
184 .n = { .min = 3, .max = 6 },
185 .m = { .min = 2, .max = 256 },
186 .m1 = { .min = 0, .max = 0 },
187 .m2 = { .min = 0, .max = 254 },
188 .p = { .min = 7, .max = 112 },
189 .p1 = { .min = 1, .max = 8 },
197 * the range value for them is (actual_value - 2).
200 .dot = { .min = 25000, .max = 350000 },
201 .vco = { .min = 1760000, .max = 3510000 },
202 .n = { .min = 1, .max = 5 },
203 .m = { .min = 79, .max = 127 },
204 .m1 = { .min = 12, .max = 22 },
205 .m2 = { .min = 5, .max = 9 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8 },
213 .dot = { .min = 25000, .max = 350000 },
214 .vco = { .min = 1760000, .max = 3510000 },
215 .n = { .min = 1, .max = 3 },
216 .m = { .min = 79, .max = 118 },
217 .m1 = { .min = 12, .max = 22 },
218 .m2 = { .min = 5, .max = 9 },
219 .p = { .min = 28, .max = 112 },
220 .p1 = { .min = 2, .max = 8 },
226 .dot = { .min = 25000, .max = 350000 },
227 .vco = { .min = 1760000, .max = 3510000 },
228 .n = { .min = 1, .max = 3 },
229 .m = { .min = 79, .max = 127 },
230 .m1 = { .min = 12, .max = 22 },
231 .m2 = { .min = 5, .max = 9 },
232 .p = { .min = 14, .max = 56 },
233 .p1 = { .min = 2, .max = 8 },
240 .dot = { .min = 25000, .max = 350000 },
241 .vco = { .min = 1760000, .max = 3510000 },
242 .n = { .min = 1, .max = 2 },
243 .m = { .min = 79, .max = 126 },
244 .m1 = { .min = 12, .max = 22 },
245 .m2 = { .min = 5, .max = 9 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 1760000, .max = 3510000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 79, .max = 126 },
257 .m1 = { .min = 12, .max = 22 },
258 .m2 = { .min = 5, .max = 9 },
259 .p = { .min = 14, .max = 42 },
260 .p1 = { .min = 2, .max = 6 },
272 .dot = { .min = 25000, .max = 270000 },
273 .vco = { .min = 4000000, .max = 6000000 },
274 .n = { .min = 1, .max = 7 },
275 .m1 = { .min = 2, .max = 3 },
276 .m2 = { .min = 11, .max = 156 },
277 .p1 = { .min = 2, .max = 3 },
278 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
288 .dot = { .min = 25000, .max = 540000 },
289 .vco = { .min = 4800000, .max = 6480000 },
290 .n = { .min = 1, .max = 1 },
291 .m1 = { .min = 2, .max = 2 },
292 .m2 = { .min = 24 << 22, .max = 175 << 22 },
293 .p1 = { .min = 2, .max = 4 },
298 .dot = { .min = 25000, .max = 594000 },
299 .vco = { .min = 4800000, .max = 6700000 },
300 .n = { .min = 1, .max = 1 },
301 .m1 = { .min = 2, .max = 2 },
303 .m2 = { .min = 2 << 22, .max = 255 << 22 },
304 .p1 = { .min = 2, .max = 4 },
309 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
310 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
314 * divided-down version of it.
319 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
320 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
322 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
323 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
324 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
325 DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
327 return clock->dot; in pnv_calc_dpll_params()
332 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
337 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
338 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
340 clock->vco = clock->n + 2 == 0 ? 0 : in i9xx_calc_dpll_params()
341 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
342 clock->dot = clock->p == 0 ? 0 : in i9xx_calc_dpll_params()
343 DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
345 return clock->dot; in i9xx_calc_dpll_params()
350 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
351 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
353 clock->vco = clock->n == 0 ? 0 : in vlv_calc_dpll_params()
354 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
355 clock->dot = clock->p == 0 ? 0 : in vlv_calc_dpll_params()
356 DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
358 return clock->dot; in vlv_calc_dpll_params()
363 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
364 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
366 clock->vco = clock->n == 0 ? 0 : in chv_calc_dpll_params()
367 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); in chv_calc_dpll_params()
368 clock->dot = clock->p == 0 ? 0 : in chv_calc_dpll_params()
369 DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
371 return clock->dot; in chv_calc_dpll_params()
376 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in i9xx_pll_refclk()
377 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()
379 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
380 return i915->display.vbt.lvds_ssc_freq; in i9xx_pll_refclk()
392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll_get_hw_state()
393 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()
399 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
400 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; in i9xx_dpll_get_hw_state()
403 DPLL_MD(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
405 hw_state->dpll_md = tmp; in i9xx_dpll_get_hw_state()
408 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
411 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); in i9xx_dpll_get_hw_state()
412 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); in i9xx_dpll_get_hw_state()
414 /* Mask out read-only status bits. */ in i9xx_dpll_get_hw_state()
415 hw_state->dpll &= ~(DPLL_LOCK_VLV | in i9xx_dpll_get_hw_state()
424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_crtc_clock_get()
425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_clock_get()
426 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()
427 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get()
434 fp = hw_state->fp0; in i9xx_crtc_clock_get()
436 fp = hw_state->fp1; in i9xx_crtc_clock_get()
440 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
465 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_clock_get()
480 lvds_pipe == crtc->pipe) { in i9xx_crtc_clock_get()
511 crtc_state->port_clock = port_clock; in i9xx_crtc_clock_get()
516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_crtc_clock_get()
517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_crtc_clock_get()
518 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in vlv_crtc_clock_get()
519 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_crtc_clock_get()
520 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_crtc_clock_get()
526 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
539 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
544 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_crtc_clock_get()
545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_crtc_clock_get()
546 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in chv_crtc_clock_get()
547 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_crtc_clock_get()
548 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_crtc_clock_get()
554 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
573 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
584 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
586 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
588 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
590 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
596 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
601 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
603 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
607 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
612 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
627 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
629 * single/dual channel state, if we even can. in i9xx_select_p2_div()
632 return limit->p2.p2_fast; in i9xx_select_p2_div()
634 return limit->p2.p2_slow; in i9xx_select_p2_div()
636 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
637 return limit->p2.p2_slow; in i9xx_select_p2_div()
639 return limit->p2.p2_fast; in i9xx_select_p2_div()
659 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
669 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
670 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
673 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
674 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
675 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
676 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
685 clock.p != match_clock->p) in i9xx_find_best_dpll()
688 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
717 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
725 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
727 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
728 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
729 for (clock.n = limit->n.min; in pnv_find_best_dpll()
730 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
731 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
732 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
741 clock.p != match_clock->p) in pnv_find_best_dpll()
744 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
773 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
784 max_n = limit->n.max; in g4x_find_best_dpll()
786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
788 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
789 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
790 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
791 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
792 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
793 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
802 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
833 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
840 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
847 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
868 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
871 /* min update 19.2 MHz */ in vlv_find_best_dpll()
872 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
878 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
879 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
880 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
881 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
884 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
926 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
944 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
945 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
984 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
990 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
995 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
1000 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in i965_dpll_md()
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_dpll()
1009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll()
1021 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1034 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1035 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1038 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1040 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1041 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1044 switch (clock->p2) { in i9xx_dpll()
1058 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_dpll()
1063 if (crtc_state->sdvo_tv_clock) in i9xx_dpll()
1078 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_compute_dpll()
1079 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
1080 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()
1083 hw_state->fp0 = pnv_dpll_compute_fp(clock); in i9xx_compute_dpll()
1084 hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); in i9xx_compute_dpll()
1086 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i9xx_compute_dpll()
1087 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); in i9xx_compute_dpll()
1090 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); in i9xx_compute_dpll()
1093 hw_state->dpll_md = i965_dpll_md(crtc_state); in i9xx_compute_dpll()
1101 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i8xx_dpll()
1102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i8xx_dpll()
1108 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1110 if (clock->p1 == 2) in i8xx_dpll()
1113 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1114 if (clock->p2 == 4) in i8xx_dpll()
1117 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_dpll()
1118 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_dpll()
1126 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_dpll()
1149 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()
1151 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i8xx_compute_dpll()
1152 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); in i8xx_compute_dpll()
1154 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); in i8xx_compute_dpll()
1157 static int hsw_crtc_compute_clock(struct intel_atomic_state *state, in hsw_crtc_compute_clock() argument
1160 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_compute_clock()
1162 intel_atomic_get_new_crtc_state(state, crtc); in hsw_crtc_compute_clock()
1164 intel_get_crtc_new_encoder(state, crtc_state); in hsw_crtc_compute_clock()
1171 ret = intel_compute_shared_dplls(state, crtc, encoder); in hsw_crtc_compute_clock()
1180 if (!crtc_state->has_pch_encoder) in hsw_crtc_compute_clock()
1181 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in hsw_crtc_compute_clock()
1186 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, in hsw_crtc_get_shared_dpll() argument
1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_get_shared_dpll()
1191 intel_atomic_get_new_crtc_state(state, crtc); in hsw_crtc_get_shared_dpll()
1193 intel_get_crtc_new_encoder(state, crtc_state); in hsw_crtc_get_shared_dpll()
1199 return intel_reserve_shared_dplls(state, crtc, encoder); in hsw_crtc_get_shared_dpll()
1202 static int dg2_crtc_compute_clock(struct intel_atomic_state *state, in dg2_crtc_compute_clock() argument
1206 intel_atomic_get_new_crtc_state(state, crtc); in dg2_crtc_compute_clock()
1208 intel_get_crtc_new_encoder(state, crtc_state); in dg2_crtc_compute_clock()
1215 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in dg2_crtc_compute_clock()
1220 static int mtl_crtc_compute_clock(struct intel_atomic_state *state, in mtl_crtc_compute_clock() argument
1224 intel_atomic_get_new_crtc_state(state, crtc); in mtl_crtc_compute_clock()
1226 intel_get_crtc_new_encoder(state, crtc_state); in mtl_crtc_compute_clock()
1234 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()
1236 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in mtl_crtc_compute_clock()
1244 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_fb_cb_factor()
1245 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ilk_fb_cb_factor()
1248 ((intel_panel_use_ssc(display) && i915->display.vbt.lvds_ssc_freq == 100000) || in ilk_fb_cb_factor()
1252 if (crtc_state->sdvo_tv_clock) in ilk_fb_cb_factor()
1260 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1279 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_dpll()
1280 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_dpll()
1290 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1312 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_dpll()
1319 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1321 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1323 switch (clock->p2) { in ilk_dpll()
1337 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_dpll()
1352 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in ilk_compute_dpll()
1355 hw_state->fp0 = ilk_dpll_compute_fp(clock, factor); in ilk_compute_dpll()
1356 hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor); in ilk_compute_dpll()
1358 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); in ilk_compute_dpll()
1361 static int ilk_crtc_compute_clock(struct intel_atomic_state *state, in ilk_crtc_compute_clock() argument
1364 struct intel_display *display = to_intel_display(state); in ilk_crtc_compute_clock()
1365 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in ilk_crtc_compute_clock()
1367 intel_atomic_get_new_crtc_state(state, crtc); in ilk_crtc_compute_clock()
1373 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
1378 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1380 dev_priv->display.vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
1381 refclk = dev_priv->display.vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
1399 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1400 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1401 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1402 return -EINVAL; in ilk_crtc_compute_clock()
1404 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in ilk_crtc_compute_clock()
1406 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1407 &crtc_state->dpll); in ilk_crtc_compute_clock()
1409 ret = intel_compute_shared_dplls(state, crtc, NULL); in ilk_crtc_compute_clock()
1413 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1414 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in ilk_crtc_compute_clock()
1419 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, in ilk_crtc_get_shared_dpll() argument
1423 intel_atomic_get_new_crtc_state(state, crtc); in ilk_crtc_get_shared_dpll()
1426 if (!crtc_state->has_pch_encoder) in ilk_crtc_get_shared_dpll()
1429 return intel_reserve_shared_dplls(state, crtc, NULL); in ilk_crtc_get_shared_dpll()
1434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_dpll()
1440 if (crtc->pipe != PIPE_A) in vlv_dpll()
1452 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_compute_dpll()
1454 hw_state->dpll = vlv_dpll(crtc_state); in vlv_compute_dpll()
1455 hw_state->dpll_md = i965_dpll_md(crtc_state); in vlv_compute_dpll()
1460 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_dpll()
1466 if (crtc->pipe != PIPE_A) in chv_dpll()
1478 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_compute_dpll()
1480 hw_state->dpll = chv_dpll(crtc_state); in chv_compute_dpll()
1481 hw_state->dpll_md = i965_dpll_md(crtc_state); in chv_compute_dpll()
1484 static int chv_crtc_compute_clock(struct intel_atomic_state *state, in chv_crtc_compute_clock() argument
1488 intel_atomic_get_new_crtc_state(state, crtc); in chv_crtc_compute_clock()
1492 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1493 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1494 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1495 return -EINVAL; in chv_crtc_compute_clock()
1497 chv_calc_dpll_params(refclk, &crtc_state->dpll); in chv_crtc_compute_clock()
1505 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1506 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in chv_crtc_compute_clock()
1511 static int vlv_crtc_compute_clock(struct intel_atomic_state *state, in vlv_crtc_compute_clock() argument
1515 intel_atomic_get_new_crtc_state(state, crtc); in vlv_crtc_compute_clock()
1519 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1520 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1521 refclk, NULL, &crtc_state->dpll)) in vlv_crtc_compute_clock()
1522 return -EINVAL; in vlv_crtc_compute_clock()
1524 vlv_calc_dpll_params(refclk, &crtc_state->dpll); in vlv_crtc_compute_clock()
1532 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1533 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in vlv_crtc_compute_clock()
1538 static int g4x_crtc_compute_clock(struct intel_atomic_state *state, in g4x_crtc_compute_clock() argument
1541 struct intel_display *display = to_intel_display(state); in g4x_crtc_compute_clock()
1542 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in g4x_crtc_compute_clock()
1544 intel_atomic_get_new_crtc_state(state, crtc); in g4x_crtc_compute_clock()
1550 refclk = dev_priv->display.vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
1551 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
1570 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1571 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1572 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1573 return -EINVAL; in g4x_crtc_compute_clock()
1575 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in g4x_crtc_compute_clock()
1577 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1578 &crtc_state->dpll); in g4x_crtc_compute_clock()
1580 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1583 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in g4x_crtc_compute_clock()
1588 static int pnv_crtc_compute_clock(struct intel_atomic_state *state, in pnv_crtc_compute_clock() argument
1591 struct intel_display *display = to_intel_display(state); in pnv_crtc_compute_clock()
1592 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in pnv_crtc_compute_clock()
1594 intel_atomic_get_new_crtc_state(state, crtc); in pnv_crtc_compute_clock()
1600 refclk = dev_priv->display.vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
1601 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
1611 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
1612 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1613 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1614 return -EINVAL; in pnv_crtc_compute_clock()
1616 pnv_calc_dpll_params(refclk, &crtc_state->dpll); in pnv_crtc_compute_clock()
1618 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1619 &crtc_state->dpll); in pnv_crtc_compute_clock()
1621 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1622 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in pnv_crtc_compute_clock()
1627 static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, in i9xx_crtc_compute_clock() argument
1630 struct intel_display *display = to_intel_display(state); in i9xx_crtc_compute_clock()
1631 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i9xx_crtc_compute_clock()
1633 intel_atomic_get_new_crtc_state(state, crtc); in i9xx_crtc_compute_clock()
1639 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
1640 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
1650 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
1651 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1652 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1653 return -EINVAL; in i9xx_crtc_compute_clock()
1655 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i9xx_crtc_compute_clock()
1657 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1658 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1660 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1663 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i9xx_crtc_compute_clock()
1668 static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, in i8xx_crtc_compute_clock() argument
1671 struct intel_display *display = to_intel_display(state); in i8xx_crtc_compute_clock()
1672 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i8xx_crtc_compute_clock()
1674 intel_atomic_get_new_crtc_state(state, crtc); in i8xx_crtc_compute_clock()
1680 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
1681 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
1693 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
1694 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1695 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1696 return -EINVAL; in i8xx_crtc_compute_clock()
1698 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i8xx_crtc_compute_clock()
1700 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1701 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1703 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1704 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i8xx_crtc_compute_clock()
1751 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, in intel_dpll_crtc_compute_clock() argument
1754 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_compute_clock()
1756 intel_atomic_get_new_crtc_state(state, crtc); in intel_dpll_crtc_compute_clock()
1759 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_compute_clock()
1761 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
1762 sizeof(crtc_state->dpll_hw_state)); in intel_dpll_crtc_compute_clock()
1764 if (!crtc_state->hw.enable) in intel_dpll_crtc_compute_clock()
1767 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1769 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1770 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_compute_clock()
1777 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, in intel_dpll_crtc_get_shared_dpll() argument
1780 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_get_shared_dpll()
1782 intel_atomic_get_new_crtc_state(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1785 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_get_shared_dpll()
1786 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1788 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1791 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1794 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1796 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1797 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_get_shared_dpll()
1808 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1810 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1812 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1814 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1816 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1818 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1820 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1822 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1824 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1826 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_enable_pll()
1841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1842 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_enable_pll()
1843 enum pipe pipe = crtc->pipe; in i9xx_enable_pll()
1846 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1852 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); in i9xx_enable_pll()
1853 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); in i9xx_enable_pll()
1861 hw_state->dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1862 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1870 hw_state->dpll_md); in i9xx_enable_pll()
1877 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1882 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1919 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_prepare_pll()
1920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_prepare_pll()
1921 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
1922 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in vlv_prepare_pll()
1923 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_prepare_pll()
1924 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
1947 tmp = DPIO_M1_DIV(clock->m1) | in vlv_prepare_pll()
1948 DPIO_M2_DIV(clock->m2) | in vlv_prepare_pll()
1949 DPIO_P1_DIV(clock->p1) | in vlv_prepare_pll()
1950 DPIO_P2_DIV(clock->p2) | in vlv_prepare_pll()
1951 DPIO_N_DIV(clock->n) | in vlv_prepare_pll()
1966 if (crtc_state->port_clock == 162000 || in vlv_prepare_pll()
2006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _vlv_enable_pll()
2007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
2008 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in _vlv_enable_pll()
2009 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
2011 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _vlv_enable_pll()
2016 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
2022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_enable_pll()
2023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
2024 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_enable_pll()
2025 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
2027 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in vlv_enable_pll()
2034 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2036 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2041 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md); in vlv_enable_pll()
2047 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_prepare_pll()
2048 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_prepare_pll()
2049 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2050 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in chv_prepare_pll()
2051 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_prepare_pll()
2055 m2_frac = clock->m2 & 0x3fffff; in chv_prepare_pll()
2062 DPIO_CHV_P1_DIV(clock->p1) | in chv_prepare_pll()
2063 DPIO_CHV_P2_DIV(clock->p2) | in chv_prepare_pll()
2066 /* Feedback post-divider - m2 */ in chv_prepare_pll()
2068 DPIO_CHV_M2_DIV(clock->m2 >> 22)); in chv_prepare_pll()
2070 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
2097 if (clock->vco == 5400000) { in chv_prepare_pll()
2102 } else if (clock->vco <= 6200000) { in chv_prepare_pll()
2107 } else if (clock->vco <= 6480000) { in chv_prepare_pll()
2136 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _chv_enable_pll()
2137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
2138 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in _chv_enable_pll()
2139 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in _chv_enable_pll()
2140 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in _chv_enable_pll()
2141 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
2159 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _chv_enable_pll()
2163 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
2169 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_enable_pll()
2170 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
2171 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_enable_pll()
2172 enum pipe pipe = crtc->pipe; in chv_enable_pll()
2174 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in chv_enable_pll()
2181 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
2183 if (hw_state->dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
2197 hw_state->dpll_md); in chv_enable_pll()
2199 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; in chv_enable_pll()
2205 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
2210 hw_state->dpll_md); in chv_enable_pll()
2216 * vlv_force_pll_on - forcibly enable just the PLL
2228 struct intel_display *display = &dev_priv->display; in vlv_force_pll_on()
2234 return -ENOMEM; in vlv_force_pll_on()
2236 crtc_state->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
2237 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()
2238 crtc_state->dpll = *dpll; in vlv_force_pll_on()
2239 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); in vlv_force_pll_on()
2249 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); in vlv_force_pll_on()
2299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
2300 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
2301 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
2308 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
2316 * vlv_force_pll_off - forcibly disable just the PLL
2331 /* Only for pre-ILK configs */
2333 enum pipe pipe, bool state) in assert_pll() argument
2335 struct intel_display *display = &dev_priv->display; in assert_pll()
2339 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_pll()
2340 "PLL state assertion failure (expected %s, current %s)\n", in assert_pll()
2341 str_on_off(state), str_on_off(cur_state)); in assert_pll()