37 	} dot, vco, n, m, m1, m2, p, p1;  member
46 	.vco = { .min = 908000, .max = 1512000 },
59 	.vco = { .min = 908000, .max = 1512000 },
72 	.vco = { .min = 908000, .max = 1512000 },
85 	.vco = { .min = 1400000, .max = 2800000 },
98 	.vco = { .min = 1400000, .max = 2800000 },
112 	.vco = { .min = 1750000, .max = 3500000},
127 	.vco = { .min = 1750000, .max = 3500000},
140 	.vco = { .min = 1750000, .max = 3500000 },
154 	.vco = { .min = 1750000, .max = 3500000 },
168 	.vco = { .min = 1700000, .max = 3500000 },
183 	.vco = { .min = 1700000, .max = 3500000 },
201 	.vco = { .min = 1760000, .max = 3510000 },
214 	.vco = { .min = 1760000, .max = 3510000 },
227 	.vco = { .min = 1760000, .max = 3510000 },
241 	.vco = { .min = 1760000, .max = 3510000 },
254 	.vco = { .min = 1760000, .max = 3510000 },
273 	.vco = { .min = 4000000, .max = 6000000 },
289 	.vco = { .min = 4800000, .max = 6480000 },
299 	.vco = { .min = 4800000, .max = 6700000 },
310  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
322 	clock->vco = clock->n == 0 ? 0 :  in pnv_calc_dpll_params()
325 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in pnv_calc_dpll_params()
340 	clock->vco = clock->n + 2 == 0 ? 0 :  in i9xx_calc_dpll_params()
343 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in i9xx_calc_dpll_params()
353 	clock->vco = clock->n == 0 ? 0 :  in vlv_calc_dpll_params()
356 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in vlv_calc_dpll_params()
366 	clock->vco = clock->n == 0 ? 0 :  in chv_calc_dpll_params()
369 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in chv_calc_dpll_params()
607 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)  in intel_pll_is_valid()
1124 	 *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock  in i8xx_dpll()
2097 	if (clock->vco == 5400000) {  in chv_prepare_pll()
2102 	} else if (clock->vco <= 6200000) {  in chv_prepare_pll()
2107 	} else if (clock->vco <= 6480000) {  in chv_prepare_pll()